cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 150

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

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The bits that can cause a stall in master mode are:
T Negative acknowledge after sending a byte
T ACBST.SDAST bit is set.
T If the ACBCTL1.STASTRE bit is set, after a successful
Repeated Start
A repeated start is performed when this device is already
the bus master (ACBST.MASTER = 1). In this case, the AC-
CESS.bus is stalled and the ACB waits for the core handling
due to: negative acknowledge (ACBST.NEGACK = 1), emp-
ty buffer (ACBST.SDAST = 1), or a stop-after-start (ACB-
ST.STASTR = 1).
For a repeated start:
Master Error Detections
The ACB detects illegal Start or Stop Conditions (i.e., a
Start or Stop Condition within the data transfer, or the ac-
knowledge cycle) and a conflict on the data lines of the AC-
CESS.bus. If an illegal action is detected, the BER bit is set,
and the MASTER mode is exited (the MASTER bit is
cleared).
Bus Idle Error Recovery
When a request to become the active bus master or a re-
start operation fails, the ACBST.BER bit is set to indicate the
error. In some cases, both this device and the other device
may identify the failure and leave the bus idle. In this case,
the start sequence may not be completed and the AC-
CESS.bus may remain deadlocked.
To recover from deadlock, use the following sequence:
1. Set the ACBCTL1.START bit.
2. In master receive mode, read the last data item from
3. Follow the address send sequence, as described in
4. If the ACB was waiting for handling due to ACB-
1. Clear the ACBST.BER and ACBCST.BB bits.
2. Wait for a time-out period to check that there is no other
3. Disable, and re-enable the ACB to put it in the non-ad-
4. At this point, some of the slaves may not identify the
(ACBSTNEGACK = 1).
start (ACBST.STASTR = 1).
the ACBSDA register.
“Sending the Address Byte” on page 149.
ST.STASTR = 1, clear it only after writing the requested
address and direction to the ACBSDA register.
active master on the bus (i.e., the ACBCST.BB bit re-
mains clear).
dressed slave mode.
bus error. To recover, the ACB becomes the bus master
by issuing a Start Condition and sends an address
field; then issue a Stop Condition to synchronize all the
slaves.
150
21.2.2
A slave device waits in Idle mode for a master to initiate a
bus transaction. Whenever the ACB is enabled, and it is not
acting as a master (i.e., ACBST.MASTER = 0), it acts as a
slave device.
Once a Start Condition on the bus is detected, this device
checks whether the address sent by the current master
matches either:
T The ACBADDR.ADDR value if the ACBADDR.SAEN bit
T The ACBADDR2.ADDR value if the ACBADDR2.SAEN
T The general call address if the ACBCTL1.GCM bit is set.
This match is checked even when the ACBST.MASTER bit
is set. If a bus conflict (on SDA or SCL) is detected, the
ACBST.BER bit is set, the ACBST.MASTER bit is cleared,
and this device continues to search the received message
for a match. If an address match, or a global match, is de-
tected:
Slave Receive and Transmit
Slave Receive and Transmit are performed after a match is
detected and the data transfer direction is identified. After a
byte transfer, the ACB extends the acknowledge clock until
software reads or writes the ACBSDA register. The receive
and transmit sequence are identical to those used in the
master routine.
Slave Bus Stall
When operating as a slave, this device stalls the AC-
CESS.bus by extending the first clock cycle of a transaction
in the following cases:
Slave Error Detections
The ACB detects illegal Start and Stop Conditions on the
ACCESS.bus (i.e., a Start or Stop Condition within the data
transfer or the acknowledge cycle). When an illegal Start or
Stop Condition is detected, the BER bit is set and the
MATCH and GMATCH bits are cleared, causing the module
to be an unaddressed slave.
1. This device asserts its data pin during the acknowledge
2. The
3. If the ACBCTL1.INTEN bit is set, an interrupt is gener-
4. Software then reads the ACBST.XMIT bit to identify the
is set.
bit is set.
— The ACBST.SDAST bit is set.
— The ACBST.NMATCH, and ACBCTL1.NMINTE bits
cycle.
ACBCST.GCMTCH if it is a global call address match,
or ACBCST.ARPMATCH if it is an ARP address), and
ACBST.NMATCH in the ACBCST register are set. If the
ACBST.XMIT bit is set (i.e., slave transmit mode), the
ACBST.SDAST bit is set to indicate that the buffer is
empty.
ated if both the INTEN and NMINTE bits in the
ACBCTL1 register are set.
direction requested by the master device. It clears the
ACBST.NMATCH bit so future byte transfers are identi-
fied as data bytes.
are set.
Slave Mode
ACBCST.MATCH,
ACBCST.MATCHAF
(or