cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 40

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

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8.5.13
The FMMERASE0/FSMMERASE0 register is a byte-wide
read/write register that controls the module erase pulse
width. Software must not modify this register while a pro-
gram/erase operation is in progress (FMBUSY set). At re-
set, this register is initialized to EAh if the flash memory is
idle. The CPU bus master has read/write access to this reg-
ister.
FTMER
8.5.14
The FMEND/FSMEND register is a byte-wide read/write
register that controls the delay time after a program/erase
operation. Software must not modify this register while a
program/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 18h when the flash mem-
ory on the chip is idle. The CPU bus master has read/write
access to this register.
FTEND
8.5.15
The FMMEND/FSMMEND register is a byte-wide read/write
register that controls the delay time after a module erase op-
eration. Software must not modify this register while a pro-
gram/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 3Ch if the flash memory is
idle. The CPU bus master has read/write access to this reg-
ister.
FTMEND
7
7
7
Register 0 (FMMERASE0/FSMMERASE0)
(FMEND/FSMEND)
Register (FMMEND/FSMMEND)
Flash Memory Module Erase Time Reload
Flash Memory End Time Reload Register
Flash Memory Module Erase End Time Reload
The Flash Timing Module Erase Pulse Width
field specifies a module erase pulse width of
4096 u(FTMER + 1) prescaler output clocks.
The Flash Timing End Delay Count field spec-
ifies a delay of (FTEND + 1) prescaler output
clocks.
The Flash Timing Module Erase End Delay
Count field specifies a delay of 8 × (FTMEND
+ 1) prescaler output clocks.
FTMEND
FTMER
FTEND
0
0
0
40
8.5.16
The FMRCV/FSMRCV register is a byte-wide read/write
register that controls the recovery delay time between two
flash memory accesses. Software must not modify this reg-
ister while a program/erase operation is in progress (FM-
BUSY set). At reset, this register is initialized to 04h if the
flash memory is idle. The CPU bus master has read/write
access to this register.
FTRCV
8.5.17
The FMAR0/FSMAR0 register contains a copy of the Func-
tion Word from Information Block 0
8.5.18
The FMAR1 register contains a copy of the Protection Word
from Information Block 1. The Protection Word is sampled
at reset. The contents of the FMAR1 register define the cur-
rent Flash memory protection settings. The CPU bus mas-
ter has read-only access to this register. The FSMAR1
register has the same value as the FMAR1 register. The for-
mat is the same as the format of the Protection Word (see
Section 8.4.2).
WRPROT RDPROT ISPE EMPTY BOOTAREA 1
15
15
7
13
Flash Memory Recovery Time Reload Register
(FMRCV/FSMRCV)
Flash Memory Auto-Read Register 0 (FMAR0/
FSMAR0)
Flash Memory Auto-Read Register 1 (FMAR1/
FSMAR1)
The Flash Timing Recovery Delay Count field
specifies a delay of (FTRCV + 1) prescaler
output clocks.
12
10
Reserved
9
FTRCV
7
6
4
3
1
0
0
0