cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 93

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

16.9
The CAN module occupies 144 words in the memory ad-
dress space. This space is organized as 15 banks of 8
words per bank (plus one reserved bank) for the message
buffers and 14 words (plus 2 reserved words) for control and
status.
16.9.1
All memory locations occupied by the message buffers are
shared by the CPU and CAN module (dual-ported RAM).
The CAN module and the CPU normally have single-cycle
access to this memory. However, if an access contention oc-
curs, the access to the memory is blocked every cycle until
the contention is resolved. This internal access arbitration is
transparent to software.
Both word and byte access to the buffer RAM are allowed.
If a buffer is busy during the reception of an object (copy
process from the hidden receive buffer) or is scheduled for
transmission, the CPU has no write access to the data con-
tents of the buffer. Write to the status/control byte and read
access to the whole buffer is always enabled.
All configuration and status registers can either be access-
ed by the CAN module or the CPU only. These registers pro-
0E F0XEh
0E F0XCh
0E F0XAh
0E F0X8h
0E F0X6h
0E F0X4h
0E F0X2h
0E F0X0h
Address
CPU Access to CAN Registers/Memory
MEMORY ORGANIZATION
Register
CNSTAT
Buffer
DATA0
DATA1
DATA2
DATA3
TSTP
ID1
ID0
15
14
DLC
13
Data1[7:0]
Data3[7:0]
Data5[7:0]
Data7[7:0]
Table 40 Message Buffer Map
12
XI[28:18]/ID[10:0]
11
Reserved
10
93
vide single-cycle word and byte access without any
potential wait state.
All register descriptions within the next sections have the fol-
lowing layout:
16.9.2
The message buffers are the communication interfaces be-
tween CAN and the CPU for the transmission and the re-
ception of CAN frames. There are 15 message buffers
located at fixed addresses in the RAM location. As shown in
Table 40, each buffer consists of two words reserved for the
identifiers, 4 words reserved for up to eight CAN data bytes,
one word reserved for the time stamp, and one word for data
length code, transmit priority code, and the buffer status
codes.
15
9
CPU Access (R = read only, W = write only, R/W = read/write)
XI[14:0]
TSTP[15:0]
8
Message Buffer Organization
7
6
PRI
Bit/Field Names
Reset Value
5
/RTR
Data2[7:0]
Data4[7:0]
Data6[7:0]
Data8[7:0]
SRR
4
IDE
3
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2
XI[17:15]
ST
1
RTR
0
0