cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 37

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

8.5.3
The FM0WER register controls section-level write protec-
tion for the first half of the flash program memory. The
FMS0WER registers controls section-level write protection
for the flash data memory. Each data block is divided into 16
8K-byte sections. Each bit in the FM0WER and FSM0WER
registers controls write protection for one of these sections.
The FM0WER and FSM0WER registers are cleared after
device reset, so the flash memory is write protected after re-
set. The CPU bus master has read/write access to this reg-
isters.
FM0WEn
8.5.4
The FM1WER register controls write protection for the sec-
ond half of the program flash memory. The data block is di-
vided into 16 8K-byte sections. Each bit in the FM1WER
register controls write protection for one of these sections.
The FM1WER register is cleared after device reset, so the
flash memory is write protected after reset. The CPU bus
master has read/write access to this registers.
FM1WEn
15
15
Flash Memory 0 Write Enable Register
(FM0WER/FSM0WER)
Flash Memory 1 Write Enable Register
(FM1WER)
dress. During a read operation from an
information block, the IBD field receives the
data word read from the location specified by
the IBA address.
The Flash Memory 0 Write Enable n bits con-
trol write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
The Flash Memory 1 Write Enable n bits con-
trol write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
1
1
Bit
Bit
–
–
15
15
0
0
14
14
FM0WE
FM1WE
Logical Address Range
Logical Address Range
01 E000h
03 E000h
00 0000h
02 0000h
. . .
. . .
–
–
–
–
00 1FFFh
02 1FFFh
01 FFFFh
03 FFFFh
0
0
37
8.5.5
The FSM0WER register controls write protection for the
flash data memory. The data block is divided into 16 512-
byte sections. Each bit in the FSM0WER register controls
write protection for one of these sections. The FSM0WER
register is cleared after device reset, so the flash memory is
write protected after reset. The CPU bus master has read/
write access to this registers.
FSM0WEn
8.5.6
This register controls the basic functions of the Flash pro-
gram memory. The register is clear after device reset. The
CPU bus master has read/write access to this register.
LOWPRW
CWD
MER PER PE IENPROG DISVRF Res. CWD LOWPRW
15
7
6
Flash Data Memory 0 Write Enable Register
(FSM0WER)
Flash Memory Control Register (FMCTRL/
FSMCTRL)
5
The Flash Data Memory 0 Write Enable n bits
control write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
The Low Power Mode controls whether flash
program memory is operated in low-power
mode, which draws less current when data is
read. This is accomplished be only accessing
the flash program memory during the first half
of the clock period. The low-power mode must
not be used at System Clock frequencies
above 25 MHz, otherwise a read access may
return undefined data. This bit must not be
changed while the flash program memory is
busy being programmed or erased.
0
1
The CPU Write Disable bit controls whether
the CPU has write access to flash memory.
This bit must not be changed while FMBUSY
is set.
0
1
–
–
–
–
1
Bit
–
15
0
Normal mode.
Low-power mode.
The CPU has write access to the flash
memory
An external debugging tool is the current
“owner” of the flash memory interface, so
write accesses by the CPU are inhibited.
14
4
FSM0WE
Logical Address Range
0E 1E00h
3
0E 0000h
2
. . .
–
–
0E 01FFh
0E 1FFFh
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