mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 106

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mc68hc05x4dw

Manufacturer Part Number
mc68hc05x4dw
Description
Xc68hc705x4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Core timer registers
Core timer control
and status register
(CTCSR)
Core Timer
MC68HC05X4 Rev 1.0
Address:
If the COP circuit times out, an internal reset is generated and the normal
reset vector is fetched. COP timeout is prevented by writing a ‘0’ to bit 0
of address $1FF0. When the COP is cleared, only the final
divide-by-eight stage is cleared (see
The COP function is a mask option, enabled or disabled during device
manufacture .
CTOF — Core timer overflow
RTIF — Real time interrupt flag
Reset:
This bit is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOE is set. When
set, the bit may be cleared by writing a ‘0’ to it.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = This read-only flag is set whenever a core timer overflow
0 = No core timer overflow has occurred.
1 = This read-only flag is set when the pre-selected RTI period has
0 = The pre-selected RTI period has not elapsed.
Figure 2. Core Timer Control/Status Register (CTCSR)
$0008
CTOF
Bit 7
occurs.
elapsed. The RTI period is selected using the RT0 and RT1
bits as shown in
u
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RTIF
6
u
Core Timer
CTOE
5
0
Table
1.
RTIE
4
0
Figure
3
0
0
1).
2
0
0
RT1
1
1
Bit 0
RT0
4-ctimer
1

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