mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 52

• Manufacturer Part Number: mc68hc05x4dw
• Description: Xc68hc705x4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Real time and
core timer
(CTIMER) interrupts
Programmable
16-bit timer
interrupt
Hardware
controlled
interrupt
sequence
Resets, Interrupts and Low Power Modes
MC68HC05X4
WOI interrupt is bit 5 of the port configuration register ($03). This latch is
set by the WOI, and is cleared by writing a zero to the bit. A WOI will
cause the MPU to exit from STOP mode.
There are two different core timer interrupt flags that cause a CTIMER
interrupt whenever an interrupt is enabled and its flag becomes set,
namely RTIF and CTOF. The interrupt flags and enable bits are located
in the CTIMER control and status register (CTCSR). These interrupts will
vector to the same interrupt service routine, whose start address is
contained in memory locations $1FF8 and $1FF9 (see
control and status register (CTCSR)
To make use of the real time interrupt the RTIE bit must first be set. The
RTIF bit will then be set after the specified number of counts.
To make use of the core timer overflow interrupt the CTOFE bit must first
be set. The CTOF bit will then be set when the core timer counter
register overflows from $FF to $00.
There are three different timer interrupt flags (ICF, OCF, TOF) that
cause a timer interrupt whenever they are set and enabled. The timer
interrupt enable bits (ICIE, OCIE, TOIE) are located in the timer control
register (TCR) and the timer interrupt flag is located in the timer status
register (TSR). All three interrupts will vector to the same service routine,
whose start address is contained in memory locations $1FF4 and
$1FF5.
The following three functions (RESET, STOP, and WAIT) are not in the
strictest sense interrupts. However, they are acted upon in a similar
manner. Flowcharts for STOP and WAIT are shown in
RESET:
STOP:
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Resets, Interrupts and Low Power Modes
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A reset condition causes the program to vector to its
starting address, which is contained in memory locations
$1FFE (MSB) and $1FFF (LSB). The I-bit in the condition
code register is also set, to disable interrupts.
The STOP instruction causes the oscillator to be turned off
and the processor to ‘sleep’ until an external interrupt
and
Figure
1).
Figure
Core timer
3.
6-resets