mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 82

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mc68hc05x4dw

Manufacturer Part Number
mc68hc05x4dw
Description
Xc68hc705x4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MCAN status
register (CSTAT)
Motorola CAN
MC68HC05X4
NOTE:
Reset: with RR bit set
External Reset:
Address:
This is a read only register; only the MCAN can change its contents.
BS — Bus status
ES — Error status
TS — Transmit status
RS — Receive status
RS will not be set during a bus failure with a permanent dominant bus
level.
This bit is set (off-bus) by the MCAN when the transmit error counter
reaches 256. The MCAN will then set RR and will remain off-bus until
the CPU clears RR again. At this point the MCAN will wait for 128
successive occurrences of a sequence of 11 recessive bits before
clearing BS and resetting the read and write error counters. While
off-bus the MCAN does not take part in bus activities.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Off-bus – The MCAN is not participating in bus activities.
0 = On-bus – The MCAN is operating normally.
1 = Error – Either the read or the write error counter has reached
0 = Neither of the error counters has reached 96.
1 = Transmit – The MCAN has started to transmit a message.
0 = Idle – If the receive status bit is also clear then the MCAN is
1 = Receive – The MCAN entered receive mode from idle, or by
0 = Idle – If the transmit status bit is also clear then the MCAN is
$0022
Bit 7
BS
Figure 6. MCAN Status Register (CSTAT)
the CPU warning limit of 96.
idle; otherwise it is in receive mode.
losing arbitration during transmission.
idle; otherwise it is in transmit mode.
0
u
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ES
6
0
u
Motorola CAN
TS
5
0
0
RS
4
0
0
TCS
3
1
1
TBA
2
1
1
DO
1
0
0
RBS
Bit 0
14-mcan
0
0

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