mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 136

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mc68hc05x4dw

Manufacturer Part Number
mc68hc05x4dw
Description
Xc68hc705x4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Glossary
bit — A binary digit. A bit has a value of either logic 0 or logic 1.
branch instruction — An instruction that causes the CPU to continue processing at a memory
break module — A module in the M68HC08 Family. The break module allows software to halt
breakpoint — A number written into the break address registers of the break module. When a
break interrupt — A software interrupt caused by the appearance on the internal address bus
bus — A set of wires that transfers logic signals.
bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock
byte — A set of eight bits.
C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CGM — See “clock generator module (CGM).”
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
MC68HC0X4 Rev 1.0
location other than the next sequential address.
program execution at a programmable point in order to enter a background routine.
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
of the same value that is written in the break address registers.
frequency, f
four.
when an addition operation produces a carry out of bit 7 of the accumulator or when a
subtraction operation requires a borrow. Some logical operations and data manipulation
instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and
shifts and rotates).
CPU controls the execution of instructions.
op
, is equal to the frequency of the oscillator output, CGMXCLK, divided by
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Glossary

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