mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 119

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mc68hc05x4dw

Manufacturer Part Number
mc68hc05x4dw
Description
Xc68hc705x4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Output compare
function
Output compare
registers
11-ptimer
Address:
Address:
‘Output compare’ is a technique that may be used, for example, to
generate an output waveform, or to signal when a specific time period
has elapsed, by presetting the output compare register to the
appropriate value.
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The contents of the output compare
register are continually compared with the contents of the free-running
counter and, if a match is found, the output compare flag (OCF) in the
timer status register is set and the output level (OLVL) bit clocked to the
output level register. The output compare register values and the output
level bit should be changed after each successful comparison to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable
bit (OCIE) is set. (The free-running counter is updated every four internal
bus clock cycles.)
After a processor write cycle to the output compare register containing
the MSB at location $16, the output compare function is inhibited until
the LSB at location $17 is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB at
Reset:
Reset:
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Bit 15
Bit 7
Figure 10. Output Compare High Register (OCH)
Figure 11. Output Compare Low Register (OCL)
16-Bit Programmable Timer
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14
6
13
5
12
4
Undefined
Undefined
11
3
16-Bit Programmable Timer
10
2
MC68HC05X4 Rev 1.0
Timer functions
9
1
Bit 8
Bit 0

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