mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 83

• Manufacturer Part Number: mc68hc05x4dw
• Description: Xc68hc705x4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

15-mcan
TCS — Transmission complete status
TBA — Transmit buffer access
DO — Data overrun
This bit is cleared by the MCAN when TR becomes set. When TCS is
set it indicates that the last requested transmission was successfully
completed. If, after TCS is cleared, but before transmission begins, an
abort transmission command is issued then the transmit buffer will be
released and TCS will remain clear. TCS will then only be set after a
further transmission is both requested and successfully completed.
When clear, the transmit buffer is locked and cannot be accessed by
the CPU. This indicates that either a message is being transmitted, or
is awaiting transmission. If the CPU writes to the transmit buffer while
it is locked, then the bytes will be lost without this being signalled.
This bit is set when both receive buffers are full and there is a further
message to be stored. In this case the new message is dropped, but
the internal logic maintains the correct protocol. The MCAN does not
receive the message, but no warning is sent to the transmitting node.
The MCAN clears DO when the CPU sets the COS bit in the CCOM
register.
Note that data overrun can also be caused by a transmission, since
the MCAN will temporarily store an outgoing frame in a receive buffer
in case arbitration is lost during transmission.
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1 = Complete – Last requested transmission successfully
0 = Incomplete – Last requested transmission not complete.
1 = Released – The transmit buffer may be written to by the CPU.
0 = Locked – The CPU cannot access the transmit buffer.
1 = Overrun – Both receive buffers were full and there was another
0 = Normal operation.
completed.
message to be stored.
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Motorola CAN
Interface to the MC68HC05X4 CPU
MC68HC05X4 Rev 1.0
Motorola CAN