mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 88

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mc68hc05x4dw

Manufacturer Part Number
mc68hc05x4dw
Description
Xc68hc705x4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MCAN bus timing
register 0 (CBT0)
Motorola CAN
MC68HC05X4
NOTE:
Address:
This register can be accessed only when the RR bit in CCNTRL is set.
SJW1, SJW0 — Synchronization jump width bits
BRP5 – BRP0 — Baud rate prescaler bits
Reset:
The synchronization jump width defines the maximum number of
system clock (t
lengthened, to achieve resynchronization on data transitions on the
bus (see
These bits determine the MCAN system clock cycle time (t
is used to build up the individual bit timing, according to
the formula in
BRP5
Freescale Semiconductor, Inc.
0
0
0
0
1
:
:
For More Information On This Product,
$0026
SJW1
Bit 7
BRP4
Table
SJW1
Go to: www.freescale.com
0
0
0
0
1
:
:
Figure 10. MCAN Bus Timing 0 (CBT0)
0
0
1
1
SJW0
Table 1. Synchronization jump width
Figure
SCL
6
Motorola CAN
1).
BRP3
Table 2. Baud rate prescaler
) cycles by which a bit may be shortened, or
0
0
0
0
1
:
:
11.
SJW0
BRP5
5
0
1
0
1
BRP2
0
0
0
0
1
:
:
BRP4
4
Undefined
Synchronization jump width
BRP1
0
0
1
1
1
:
:
BRP3
2 t
3 t
4 t
3
1 t
SCL
SCL
SCL
BRP0
SCL
0
1
0
1
1
:
:
cycles
cycles
cycles
cycle
BRP2
2
Prescaler value (P)
BRP1
1
Table 2
SCL
64
1
2
3
4
:
:
), which
BRP0
Bit 0
20-mcan
and

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