mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 77

• Manufacturer Part Number: mc68hc05x4dw
• Description: Xc68hc705x4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MCAN control
register (CCNTRL)
9-mcan
NOTE:
Reset: with RR bit set
External Reset:
Address:
This register may be read or written to by the MCU; only the RR bit is
affected by the MCAN.
Only the RR bit in this register can be written when the RR bit is set.
MODE — Undefined mode
SPD — Speed mode
OIE — Overrun interrupt enable
EIE — Error interrupt enable
TIE — Transmit interrupt enable
This bit must never be set by the CPU as this would result in the
transmit and receive buffers being mapped out of memory. The bit is
cleared on reset, and should be left in this state for normal operation.
Freescale Semiconductor, Inc.
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1 = Slow – Bus line transitions from both ‘recessive’ to ‘dominant’ and
0 = Fast – Only transitions from ‘recessive’ to ‘dominant’ will be
1 = Enabled – The CPU will get an interrupt request whenever the
0 = Disabled – The CPU will get no overrun interrupt request.
1 = Enabled – The CPU will get an interrupt request whenever the
0 = Disabled – The CPU will get no error interrupt request.
1 = Enabled – The CPU will get an interrupt request whenever a
0 = Disabled – The CPU will get no transmit interrupt request.
MODE
Figure 4. MCAN Control Register (CCNTRL)
$0020
Bit 7
from ‘dominant’ to ‘recessive’ will be used for resynchronization.
used for resynchronization.
Overrun Status bit gets set.
error status or bus status bits in the CSTAT register change.
message has been successfully transmitted, or when the transmit
buffer is accessible again following an ABORT command.
0
0
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SPD
6
u
u
Motorola CAN
5
-
-
OIE
4
u
u
Interface to the MC68HC05X4 CPU
EIE
3
u
u
TIE
2
u
u
MC68HC05X4 Rev 1.0
RIE
1
u
u
Motorola CAN
Bit 0
RR
1
1