mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet - Page 66

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mc68hc05x4dw

Manufacturer Part Number
mc68hc05x4dw
Description
Xc68hc705x4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Port registers
Port A data
register (PADR)
Port B data register
(PBDR)
Port configuration
register (PCR)
Parallel input/output ports
MC68HC05X4 Rev 1.0
NOTE:
Address:
The following sections explain in detail the individual bits in the data and
control registers associated with the ports.
Each bit can be configured as input or output via the corresponding data
direction bit in the port A DDR.
Reset does not affect the state of this register.
If the AWPS bit in the PCR is set then this location becomes the port A
wired-OR interrupt enable register. Writing a ‘1’ to any bit enables WOI
on the corresponding port A line.
Each bit can be configured as input or output via the corresponding data
direction bit in the port B DDR.
Reset does not affect the state of this register.
WOIF — Wired-OR interrupt flag
TIMEN — Timer enable
CAF — Indicates when MCAN is asleep
Reset:
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Indicates that a wired-OR interrupt has been received. A CPU
0 = The flag is cleared by writing a ‘0’ to it.
$0005
Bit 7
interrupt request is generated if WOIE is set on port A or port B.
-
Figure 2. Port Configuration Register (PCR)
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Parallel input/output ports
6
-
WOIF
5
0
TIMEN
4
0
CAF
3
0
BPDE0
2
0
BWE
1
0
AWPS
Bit 0
0
4-ports

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