w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 47

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

UART Register Bit Map, continued.
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit
3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit
is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as
the transmitter will be detected.
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
BDLAB
BDLAB
ADDRESS BASE
+ 5
+ 6
+ 7
+ 0
= 1
+ 1
= 1
REGISTER
Latch High
Handshake
Latch Low
Baudrate
Baudrate
Register
Register
Register
Defined
Divisor
Divisor
Status
Status
UART
User
UDR
USR
HSR
BHL
BLL
Toggling
(TCTS)
Ready
(RDR)
RBR
Data
CTS
Bit 0
Bit 0
Bit 8
0
Toggling
Overrun
(TDSR)
(OER)
Error
DSR
Bit 1
Bit 1
Bit 9
1
BIT NUMBER
RI Falling
Parity Bit
(PBER)
- 47 -
(FERI)
Bit 10
Edge
Error
Bit 2
Bit 2
2
W83L517D/W83L517D-F
Toggling
No Stop
(NSER)
(TDCD)
Bit 11
Error
DCD
Bit 3
Bit 3
Bit
3
Publication Release Date: May 23, 2005
Detecte
to Send
(SBD)
(CTS)
Silent
Bit 12
Clear
Byte
Bit 4
Bit 4
4
d
(TBRE)
Ready
Empty
(DSR)
Bit 13
TBR
Data
Bit 5
Bit 5
Set
5
Indicator
(TSRE)
Empty
Bit 14
Ring
TSR
Bit 6
Bit 6
(RI)
6
Revision 1.0
RX FIFO
Indicatio
n (RFEI)
Carrier
Detect
(DCD)
Bit 15
Error
Data
Bit 7
Bit 7
**
7