w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 67

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

8.3
8.3.1
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any register which is
meaningful in legacy SIR/ASK-IR.
Bit 3
Bit 2:
Bit 1:
Bit 0:
SET & REGISTER
ADDRESS OFFSET
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
Set1 - Legacy Baud Rate Divisor Register
Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
MIR, FIR Modes:
MIR, FIR Modes:
MIR, FIR, Remote IR Modes:
0
1
2
3
4
5
6
7
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure od PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
This bit should be set to 1, if used in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Reserved.
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends remain in receiver FIFO.
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
ADVANCED MODE
REGISTER NAME
UDR/ESCR
UCR/SSR
ISR/UFR
HCR
USR
HSR
BHL
BLL
Bit 0, 5, 7
Bit 7~5
Bit 2, 3
DIS_BACK=×
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Interrupt Status or IR FIFO Control Register
Baud Rate Divisor Latch (High Byte)
Baud Rate Divisor Latch (Low Byte)
IR Control or Sets Select Register
W83L517D/W83L517D-F
Handshake Control Register
Handshake Status Register
REGISTER DESCRIPTION
User Defined Register
IR Status Register
Publication Release Date: May 23, 2005
LEGACY MODE
DIS_BACK=0
Bit 5, 7
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Revision 1.0