w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 76

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

8.7.1
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
8.7.2
These registers control flow control mode operation as shown in the following table.
8.7.3
Writing this register selects Register Set. Reading this register returns ECH.
Bit 2:
Bit 1:
Bit 0:
Bit 7~5
Bit 4:
Bit 3:
FC_MD
Default Value
Reset
Value
REG.
REG.
SSR
Set5.Reg2 - Flow Control Mode Operation (FC_MD)
Set5.Reg3 - Sets Select Register (SSR)
Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced HSR
(Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allows user to swap DMA channel for transmitter or receiver when flow control
is enforced.
FC_MD2 FC_MD1 FC_MD0
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
BIT 7
0
SSR7
BIT 7
FC_DSW
1
0
1
BIT 6
0
SSR6
BIT 6
1
BIT 5
SSR5
0
BIT 5
1
Next Mode After Flow Control Occurred
BIT 4
- 76 -
SSR4
BIT 4
0
-
0
Transmitter Channel
Receiver Channel
W83L517D/W83L517D-F
FC_DSW
BIT 3
SSR3
BIT 3
0
1
EN_FD
BIT 2
SSR2
BIT 2
0
1
EN_BRFC EN_FC
BIT 1
SRR1
BIT 1
0
0
SRR0
BIT 0
BIT 0
0
0