w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 54

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w83l517g

Manufacturer Part Number
w83l517g
Description
Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
Manufacturer
Winbond Electronics Corp America
Datasheet
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
7.2.8
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table in the next page illustrates the use of the baud generator with a frequency of
1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud
generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed
mode, the data transmission rate can be as high as 1.5M bps.
7.2.9
This is a temporary register that can be accessed and defined by the user.
PRE-DIV: 13
1.8461M HZ
134.5
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
50
75
Programmable Baud Generator (BLL/BHL) (Read/Write)
User-defined Register (UDR) (Read/Write)
PRE-DIV:1.625
14.769M HZ
14400
16000
19200
28800
38400
57600
76800
1076
1200
2400
4800
9600
400
600
880
BAUD RATE FROM DIFFERENT PRE-DIVIDER
TABLE 7-5 BAUD RATE TABLE
PRE-DIV: 1.0
24M HZ
124800
1478.5
15600
23400
26000
31200
46800
62400
93600
1430
1950
3900
7800
650
975
- 54 -
USED TO GENERATE
DECIMAL DIVISOR
16X CLOCK
W83L517D/W83L517D-F
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
16
-1. The output frequency of
ERROR PERCENTAGE
BETWEEN DESIRED
AND ACTUAL
0.099%
0.18%
0.53%
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