w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 75

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

8.6.4
These are combined to be a 13-bit register. Writing these registers programs the transmitter frame
length of a package.
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame
length if the transmitted data is larger than the programmed frame length. When these registers are
read, they will return the number of bytes which is not transmitted from a frame length programmed.
8.6.5
These are combined to be a 13-bit register and up counter. The length of receiver frame will be
limited to the programmed frame length. If the received frame length is larger than the programmed
receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously,
the receiver will not receive any more data to RX FIFO until the next start flag of the next frame, which
is defined in the physical layer IrDA 1.1. Reading these registers returns the number of received data
bytes of a frame from the receiver.
8.7
ADDRESS OFFSET
Reset Value
Reset Value
Reset Value
Reset Value
RFRLH
TFRLH
RFRLL
TFRLL
REG.
REG.
Set 5 - Flow control and IR control and Frame Status FIFO registers
Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH)
Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
0
1
2
3
4
5
6
7
BIT 7
BIT 7
bit 7
bit 7
0
0
-
-
-
-
REGISTER NAME
These registers are only valid when APM=1 (automatic package mode,
BIT 6
BIT 6
bit 6
bit 6
RFRLFH
0
0
RFRLFL
IRCFG1
-
-
-
-
FC_MD
FCBHL
FS_FO
FCBLL
SSR
BIT 5
BIT 5
bit 5
bit 5
0
0
-
-
-
-
Flow Control Baud Rate Divisor Latch Register (Low Byte)
Flow Control Baud Rate Divisor Latch Register (High
Byte)
Flow Control Mode Operation
Sets Select Register
Infrared Configure Register
Frame Status FIFO Register
Receiver Frame Length FIFO Low Byte
Receiver Frame Length FIFO High Byte
bit 12
bit 12
BIT 4
BIT 4
bit 4
bit 4
- 75 -
0
0
0
0
W83L517D/W83L517D-F
bit 11
bit 11
REGISTER DESCRIPTION
BIT 3
BIT 3
bit 3
bit3
0
0
0
0
Publication Release Date: May 23, 2005
bit 10
bit 10
BIT 2
BIT 2
bit 2
bit 2
0
0
0
0
BIT 1
BIT 1
bit 1
bit 9
bit 1
bit 9
0
0
0
0
Revision 1.0
BIT 0
BIT 0
bit 0
bit 8
bit 0
bit 8
0
0
0
0