w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 53

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
7.2.7
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
Bit
3
0
0
0
1
0
0
Bit
2
0
1
1
1
0
0
Interrupt Control Register (ICR) (Read/Write)
ISR
Bit
1
1
0
1
0
0
0
7
0
Bit
0
1
0
0
0
0
0
0
6
Interrupt
Second
Second
5
0
priority
Fourth
Third
First
TABLE 7-4 INTERRUPT CONTROL FUNCTION
-
4
0
3
TBR Empty
Handshake
FIFO Data
RBR Data
2
Interrupt
Receive
Timeout
Ready
Status
UART
status
Type
1
-
0
INTERRUPT SET AND FUNCTION
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
1. OER = 1
3. NSER = 1 4. SBD = 1
1. TCTS = 1 2. TDSR = 1
3. FERI = 1
- 53 -
for 4 characters period of
Data present in RX FIFO
time since last access of
2. FIFO interrupt active
No Interrupt pending
1. RBR data ready
Interrupt Source
level reached
TBR empty
W83L517D/W83L517D-F
RX FIFO.
2. PBER =1
4. TDCD = 1
Publication Release Date: May 23, 2005
1. Read RBR
2. Read RBR until
FIFO data under active
level
1. Write data into TBR
2. Read ISR (if priority
is third)
Clear Interrupt
Read USR
Read RBR
Read HSR
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Revision 1.0