w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 94

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

9.2.5
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of
cycle to be performed and the data to be output to the host CPU.
9.2.6
Data Port (R/W)
Status
(Read)
Control Swapper
(Read)
Control
(Write)
EPP Address Port
R/W)
EPP Data Port 0
(R/W)
EPP Data Port 1
(R/W)
EPP Data Port 2
(R/W)
EPP Data Port 3
(R/W)
REGISTER
EPP Data Port 0-3
Bit Map of Parallel Port and EPP Registers
Buffer
Latch
BUSY#
PD7
PD7
PD7
PD7
PD7
PD7
7
1
1
ACK#
PD6
PD6
PD6
PD6
PD6
PD6
7
6
1
1
6
PD5
PD5
PD5
PD5
PD5
PD5
DIR
PE
5
1
5
4
IRQEN
SLCT
PD4
PD4
PD4
PD4
PD4
PD4
IRQ
- 94 -
4
3
2
ERROF#
W83L517D/W83L517D-F
1
SLIN
SLIN
PD3
PD3
PD3
PD3
PD3
PD3
3
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INIT#
INIT#
PD2
PD2
PD2
PD2
PD2
PD2
2
1
IOR#
AUTOFD#
AUTOFD#
PD1
PD1
PD1
PD1
PD1
PD1
causes an EPP read
1
1
STROBE#
STROBE#
TMOUT
PD0
PD0
PD0
PD0
PD0
PD0
0