w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 59

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

8.2.3
Interrupt Status Register (Read Only)
Legacy IR:
This register reflects the Legacy IR interrupt status, which is encoded by different interrupt sources
into 3 bits.
Bit 7, 6:
Bit 5, 4:
Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical 1
when a time-out interrupt is pending.
Bit 2, 1:
below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to logical 0.
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
Advanced IR
Bit
3
0
0
0
1
0
Legacy IR
Reset Value
MODE
Bit
2
1
0
0
1
1
Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)
ISR
Bit
1
0
1
0
0
1
FIFO Enable FIFO Enable
These two bits are set to a logical 1 when UFR bit 0 = 1.
These two bits are always logical 0.
These bits identify the priority level of the pending interrupt, as shown in the table
TMR_I
Bit
0
1
0
0
0
0
B7
0
Interrupt
Second
Second
priority
Third
First
TABLE: INTERRUPT CONTROL FUNCTION
-
FSF_I
B6
0
TBR Empty
IR Receive
FIFO Data
RBR Data
Time-out
Interrupt
Status
Ready
Type
-
TXTH_I DMA_I HS_I
INTERRUPT SET AND FUNCTION
B5
0
1
- 59 -
1. OER = 1
3. NSER = 1 4. SBD = 1
for 4 characters period of
Data present in RX FIFO
time since last access of
2. FIFO interrupt active
No Interrupt pending
1. RBR data ready
B4
0
0
Interrupt Source
level reached
W83L517D/W83L517D-F
TBR empty
RX FIFO.
IID2
B3
0
2. PBER =1
Publication Release Date: May 23, 2005
FEND_I
USR_I/
IID1
B2
0
FIFO
TXEMP_I RXTH_I
2. Read RBR until
1. Write data into
priority is third)
2. Read ISR (if
Clear Interrupt
1. Read RBR
IID0
active level
B1
Read USR
Read RBR
1
TBR
data under
-
Revision 1.0
B0
IP
0