tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 134

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers
9.1 SPE Mapper Register Descriptions
This section gives a brief description of each register bit and its functionality. The abbreviations after each register
indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).
Table 144. SPE_VERSION_R, SPE Version and Identification Register (RO)
Table 145. SPE_ONESHOT, One-Shot (R/W)
Note: In Table 122, the mask bits for these delta and event bits are in
Table 146. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW)
134
Address
0x30003
Address
Address
0x30000
0x30002
monitor values are in
15:7
15:11
Bit
10:8
15:5
6
5
4
3
2
1
0
Bit
7:0
Bit
4
3
2
1
0
SPE_TPOAC_PE
SPE_VERSION[2:0] Block Version Number. Block version register will change
SPE_RDATA_PE
SPE_K3DMOND
SPE_N1DMOND
SPE_C2DMOND
SPE_F2DMOND
SPE_F3DMOND
SPE_BIPOL_ERR
SPEMPR_ID[7:0]
SPE_SDCLEAR
SPE_SFCLEAR
SPE_SDSET
SPE_SFSET
Name
Name
Name
Table
—
—
—
152.
(continued)
Reserved.
Received Data Parity Error Event. Event bit indicates a parity
error was detected on the incoming data.
Transmit POAC Parity Error Event. Event bit indicates a parity
error was detected on the incoming POAC.
K3 Data Monitor Delta Bit. The mask bit is SPE_K3DMONM.
N1 Data Monitor Delta Bit. The mask bit is SPE_N1DMONM.
C2 Data Monitor Delta Bit. The mask bit is SPE_C2DMONM.
F2 Data Monitor Delta Bit. The mask bit is SPE_F2DMONM.
F3 Data Monitor Delta Bit. The mask bit is SPE_F3DMONM.
Reserved.
each time the device is changed.
Block ID Number.
Reserved.
Bipolar Violation Error. A single bipolar violation error for
DS3 output is transmitted each time this bit transitions from a
0 to 1.
Signal Fail Clear. Allows the signal fail algorithm to be forced
into the normal state.
Signal Fail Set. Allows the signal fail algorithm to be forced
into the failed state.
Signal Degrade Clear. Allows the signal degrade algorithm
to be forced into the normal state.
Signal Degrade Set. Allows the signal degrade algorithm to
be forced into the degraded state.
Function
Function
Function
Table
147, state bits are in
Agere Systems Inc.
Table
May 2001
148, and
Default
Default
Reset
Reset
0x000
Default
0x00
0x03
Reset
0x000
0x0
0
0
0
0
0
0
0
0
0
0
0
0