tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 197

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers
Tables
Table 253. M13_RDL_STATUS, Receive Data-Link Status (RO) ....................................................................... 214
Table 254. M13_RDL_DATA_R, Receive Data-Link Data (RO) ......................................................................... 214
Table 255. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO) .................................................. 214
Table 256. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO) .............................. 215
Table 257. M13_DS2_FORCE_OOF_R, DS2 Force Out of Frame (One Shot R/W) .......................................... 215
Table 258. M13_CONTROL1, Control 1 (One Shot R/W) ................................................................................... 215
Table 259. M13_CONTROL2, Control 2 (R/W) ................................................................................................... 215
Table 260. M13_CONTROL3, Control 3 (R/W) .................................................................................................. 216
Table 261. M13_SP_OFFSET_R, Sync Pulse Offset (R/W) ............................................................................... 216
Table 262. M13_SP_D_OFFSET_R, Sync Pulse D Offset (R/W) ....................................................................... 216
Table 263. M13_M12_MUX_CONTROL1_R[1—7], M12 MUX CONTROL 1 Registers [1—7] (R/W) ................ 217
Table 264. M13_M12_MUX_CONTROL2_R[1—7], M12 MUX CONTROL 2 Registers [1—7] (R/W) ................ 217
Table 265. M13_DS2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W) ............................................. 217
Table 266. M13_DS2_RSV_SEND_R, DS2 Reserve Bit Send (R/W) ................................................................ 217
Table 267. M13_DS2_MPINV_R, DS2 M Frame Alignment or Parity Error (R/W) ............................................. 218
Table 268. M13_DS2_FINV_R, DS2 Frame Error (R/W) .................................................................................... 218
Table 269. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W) ............................................................................ 218
Table 270. M13_DS2M12_EDGE_R, DS2 M12 Edge (R/W) .............................................................................. 218
Table 271. M13_DS2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W) ............................................ 218
Table 272. M13_M12_DEMUX_CONTROL1_R[1—7], M12 DeMUX Control 1 Registers [1—7] (R/W) ............ 219
Table 273. M13_M12_DEMUX_CONTROL2_R[1—7], M12 DeMUX Control 2 Registers [1—7] (R/W) ............ 219
Table 274. M13_M12_DEMUX_CONTROL3, DS2 M12 DeMUX Control 3 (R/W) ............................................. 219
Table 275. M13_DMDS2_EDGE_R, DS2 Edge for M12 DeMUX (R/W) ............................................................. 220
Table 276. M13_DS3_CONTROL1, DS3 Control 1 (R/W) .................................................................................. 220
Table 277. M13_DS3_CONTROL2, DS3 Control 2 (R/W) .................................................................................. 221
Table 278. M13_TFEAC_CONTROL, Tx FEAC Control (R/W) ........................................................................... 221
Table 279. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W) ..................................................................... 222
Table 280. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W) ..................................................................... 222
Table 281. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W) ................................................................... 222
Table 282. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W) ........................................................................ 223
Table 283. M13_RDS2_EDGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W) .................................................. 223
Table 284. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W) ............................................................................ 223
Table 285. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W) ................................................ 223
Table 286. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W) ...................................................................................... 224
Table 287. M13_RDL_CONTROL, RDL Control (R/W) ....................................................................................... 224
Table 288. M13_PM_CNT_ACT_R, Performance Counter (RO) ........................................................................ 224
Table 289. M13_DS3_FERR_CNT_R[1—2], DS3 F-Bit Error Registers (RO) .................................................... 224
Table 290. M13_DS3_FEBE_CNT_R[1—2], DS3 Far-End Block Error Registers (RO) ..................................... 225
Table 291. M13_DS3_CPERR_CNT_R[1—2], DS3 C-Bit Parity Error Registers (RO) ...................................... 225
Table 292. M13_DS3_PERR_CNT_R[1—2], DS3 P-Bit Error Registers (RO) ................................................... 225
Table 293. M13_DS2_PERR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO) ......................... 225
Table 294. M13_DS2_FERR_CNT[7—1]_R, F-Bit Error Counter Status Registers (RO) ................................... 226
Table 295. M13_BPV_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO) ..................................... 226
Table 296. M13_EXZ_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO) ..................................... 227
Table 297. M13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W) .............................................................. 227
Table 298. M13_TDL_0DATA_R[0—63], Tx Data for Path Maintenence Data-Link Buffer 0 Registers
Table 299. M13_TDL_1DATA_R[0—63], Tx Data for Path Maintenence Data-Link Buffer 1 Registers
Table 300. Register Address Map ....................................................................................................................... 228
Agere Systems Inc.
(64 Bytes x 8 Bits) (R/W) ................................................................................................................... 227
(64 Bytes x 8 Bits) (R/W) ................................................................................................................... 227
Table of Contents
(continued)
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
TMXF28155/51 Super Mapper
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