tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 248

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers
Table 312. FRM_PMGR2, Performance Monitor Global Register 2 (COR)
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 313. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
† FRM_RACFRM_RDC Standard.
248
Address*
Address*
0x80P31
0x80P32
15:14
13:11
10:8
Bit
4:3
15:0
Bit
7
6
5
2
1
0
FRM_CEPTAISM[1:0] CEPT AIS Mode.
FRM_TPERR_CT[15:0] Test Pattern Error Count Register. This register con-
FRM_CMFRFEN
FRM_CRCRFEN
FRM_FSFBEEN
FRM_ESFRAIM
FRM_DS1AISM
FRM_RDC[2:0]
FRM_RAC[2:0]
FRM_RAICLR
Name
—
Name
Reserved. Must write to 0.
CEPT Mode RAI Activation Count
CEPT Mode RAI Deactivation Count
can be set to meet various standards.
F
bit error to set the FBE status bit, FRM_FBE (
In DDS, a 0 means do not count TS24 framing and F
FBEs; a 1 means count TS24 framing and Fs as FBEs.
0 = F
1 = F
CEPT Multiframe Reframe Enable.
0 = CEPT CRC-4 multiframe reframe disabled.
1 = CEPT CRC-4 multiframe reframe enabled. A research
for multiframe alignment is initiated upon a loss of CEPT
CRC-4 multiframe alignment.
CRC Reframe Enable.
0 = CRC errors do not cause a reframe or LOF condition.
1 = The receive performance monitor will force a reframe
and LOF condition on excessive CRC errors.
00 = Option 0: G.775 section I.2; G.965 section 16.1.2.
01 = Option 1: G.775 section 5.2.
10 = Option 2: G.775 section I.2.
11 = Option 3: G.775 section I.2.
DS1 AIS Mode.
0 = Option 0: T1.231 section 6.1.2.2.3, T1.403 section H,
G.775 section 5.4.
1 = Option 1: G.775 section I.2.
ESF RAI Mode.
0 = Alternating eight ones followed by eight zeros.
1 = All ones.
Clear RAI on Reception of DS1 Idle Signal.
0 = Ignore DS1 idle signal for RAI clearing.
1 = Clear failure on reception of DS1 idle signal: ANSI
T1.231 section 6.2.2.2.1.
(continued)
S
Frame Bit Error Enable. Allows a signaling frame (F
tains the 16-bit count of test-pattern errors.
S
S
bit errors disabled.
bit errors enabled.
Function
Function
†
.
†
. RAC and RDC
Table
Agere Systems Inc.
386).
S
as
S
May 2001
)
Default
Default
Reset
Reset
001
001
00
01
0
0
0
1
1
0
0