tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 30

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
3.3.10 Test Pins
These pins are for factory test purposes only and must be connected as stated below for normal operation. They
are used to establish special configurations for testing, inserting test data, etc. For normal operation they should be
left unconnected; each is equipped with a pull-up or pull-down to the inactive (normal operation) state.
Table 16. Test Pins
Table 17. CDR Power
Table 18. LVDS Control Pins
30
AE16,
AE14
AD14
AC15
AE15
AD15
AC16
AF14
AF15
Pin
M5
N5
P5
AB12
AE12
AC11
AD12
AF12
AC9
Pin
Pin
SCAN_MODE
TSTMUX[1:0]
TSTPHASE
TSTSFTLD
TSTMODE
SCAN_EN
ETOGGLE
EXDNUP
BYPASS
Symbol
ECSEL
IDDQ
VDDA_CDR
VSSA_CDR
Symbol
Symbol
RESLO
RESHI
REF10
REF14
(continued)
Type
—
—
—
—
—
—
—
—
—
—
—
Type
Type
—
—
—
—
—
Pull down
Pull down
Pull down
Pull down
Pull down
Pulldown
Pulldown
Pulldown
Pulldown
Pull up
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Power. Isolated analog power supply VDD for CDR.
Analog Ground. Isolated analog power supply VSS for CDR.
Resistor 1, 2. A 100
these two pins as a reference for the LVDS input buffer termination.
Voltage Reference 1. 1.0 V reference voltage input.
Voltage Reference 2. 1.4 V reference voltage input.
Test Only. Scan enable (active-high).
Test Only. Serial scan input for testing (active-high).
Test Only. I
Test Only. Enables functional bypassing of the clock synthesis
with a test clock (active-high).
Test Only. Controls bypass of 32 PLL-generated phases with
32 low-speed phases, generated by test logic (active-high).
Test Only. Enables external test control of 155 MHz clock
phase selection through ETOGGLE and EXDNUP inputs
(active-high).
Test Only. Moves 155 MHz clock selection one phase per pos-
itive pulse > 20ns. Active + pulse.
Test Only. Direction of phase changes.
0 = down
1 = up.
Test Only. Enables CDR test mode.
Test Only. Enables CDR test mode shift register.
Test Only. CDR test mode output
DD
Q input (active-high).
1% resistor is should be connected between
Description
Description
Description
Agere Systems Inc.
May 2001