tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 473

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
20 M13/M23 MUX/DeMUX Block Functional Description
Once the deMUX is in-frame, the received frame bits are monitored for out-of-frame. Out-of-frame is declared
(M13_DS2_OOFy = 1) if too many errors are received in either the F bits (two errors in 4 bits when
M13_DS2_MODE = 0
M13_DS2_MODE = 1) or the M-bits (at least one error in three consecutive M frames). For testing purposes, the
user may also force the framer out-of-frame by setting M13_DS2_FORCE_OOFy
The traditional algorithm for declaring out-of-frame (two errors in 4 F bits) results in false out-of-frame approxi-
mately every 5 seconds when the bit error rate is 10
(containing 4-F bits) before declaring out-of-frame (M13_DS2_MODE = 1), the M13 normally stays in frame for
over 4four days when the bit error rate is 10
Overhead Processing. The C bits for each DS1 channel are checked for loopback requests. If the third C bit dif-
fers from the first and second C bits in the zth M-subframe for five successive DS2 frames, M13_DS1_LB_DETx
(Table
from the first two C bits in the zth M-subframe for five successive DS2 frames.
If the X bit in four consecutive frames is received as 0, the M13 sets M13_DS2_RAI_DETy
M13_DS2_RAI_DETy is set, it is not cleared until the X bit is received as 1 in four consecutive frames.
20.11.6 E1 Mode
Framer. The M12 demultiplexers determine if the input signal contains a valid frame format as specified in ITU-T
recommendation G.747. Frame alignment is declared (M13_DS2_OOFy = 0
alignment signal is received for three consecutive frames. The maximum average reframe time is 0.5 ms in the
presence of a bit error rate of 10
contains at least 1-bit error for four consecutive frames. For testing purposes, the user may also force the framer
out-of-frame by setting M13_DS2_FORCE_OOFy
Overhead Processing. The C bits for each E1 channel are checked for loopback requests. If the third Cz bit differs
from the first and second Cz bits for five successive frames, M13_DS1_LB_DETx
x = (4y – 4 + z). M13_DS1_LB_DETx is cleared when the third Cz bit does not differ from the first two Cz bits for
five successive frames.
If the RAI bit in four consecutive frames is received as 1, the M13 sets M13_DS2_RAI_DETy to 1 (
M13_DS2_RAI_DETy is set, it is not cleared until the RAI bit is received as 0 in four consecutive frames. The
received reserved bit is reported through the M13_DS2_RSV_RCVy
new value is received in four consecutive frames.
Loss of Frame and Automatic AIS Insertion. The M13_DS2_LOFy
is high continuously for 28 DS3 frame periods (approximately 3 ms). Once set, M13_DS2_LOFy is not cleared until
M13_DS2_OOFy is continuously low for 28 DS3 frame periods.
The user can provision the M13 to automatically output AIS if either bit M13_DS2_OOFy = 1 (by setting
M13_AUTO_AIS_OOF to 1), or M13_DS2_LOFy = 1 (by setting M13_AUTO_AIS_LOF to 1).
DS2 Performance Monitors. Within each M12 demultiplexer, there are two performance monitoring counters.
These counters are cleared and read as described above (see DS3 Performance Monitors on
Registers M13_DS2_FERR_CNT[7—1]_R
mode, M13_DS2_FERR_CNTy
the E1 mode, this counter increments either for each frame alignment signal bit error (when
M13_DS2_FERR_MODE = 0
error (when M13_DS2_FERR_MODE = 1).
In the E1 mode only, registers M13_DS2_PERR_CNT[7—1]_R[1—2]
Agere Systems Inc.
249) is set to 1, where x = (4y – 4 + z). M13_DS1_LB_DETx is cleared when the third C bit does not differ
(Table
274), or at least one F-bit error in four consecutive M-subframe pairs when
(Table
(Table
–3
. Out-of-frame is declared (M13_DS2_OOFy = 1) if the frame alignment signal
274)), or once for each frame alignment signal that contains at least one bit
294) increments each time an error is detected in either an F bit or M bit. In
(Table
–3
.
294) count errors in the frame alignment signal. In the DS1
(Table
–3
. By waiting for four consecutive errored M-subframe pairs
257) to 1.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table
(Table
(Table
245), which is updated only when a
241) bit is set when M13_DS2_OOFy
293) count errors in P bits.
(Table
TMXF28155/51 Super Mapper
(continued)
(Table
(Table
240)) when a correct frame
257) to 1.
249) is set to 1, where
(Table
page
Table
243) to 1. Once
472).
243). Once
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