tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 443

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description
Overhead Byte Generation (V5, J2, Z6/N2, Z7/K4, and O bits). This portion of the VTGEN logic block will gener-
ate and insert the V5, J2, Z6/N2, and Z7/K4 overhead bytes into the appropriate virtual tributary. O bits are only
accessible in the asynchronous and bit synchronous modes.
V5 Overhead Byte Format/Generation. The V5 overhead byte will be mapped as defined in
Table 559. V5 Overhead Byte Format
The following features are supported:
Table 560. BIP-2 Error Insertion Modes
Agere Systems Inc.
VT_BIP2ERR_INS[1—28][1:0] (See
When operating in tributary loopback mode (bit VT_LB_SEL[1—28] = 1 (
through transparently.
When operating in UPSR mode VT_V5_INS[1—28] = 1 (
ated and inserted while all other bits are programmed from the received LOPOH serial access channel storage.
BIP-2 will be automatically calculated and inserted. The signal label is determined based on bits
VT_TX_MAPTYPE[1—28][3:0]
AIS-V is forced by setting bit, VT_AIS_INS[1—28]
including V1~4, with all ones.
Bits VT_TX_MAPTYPE[1—28][3:0] may be programmed to insert an UNEQ-V signal label. See
Signal Label Definition on page445
User-controlled bits VT_BIP2ERR_INS[1—28][1:0]
poses. See
5. If an increment is requested, the pointer bytes, V1 and V2, are programmed with the I-bits inverted. The
6. If a decrement is requested, the pointer bytes, V1 and V2, will be programmed with the D bits inverted. The
7. The V4 byte will be programmed to the selected overhead default (microprocessor bit SMPR_OH_DEFLT) for
Bit 1
— If transmit AIS-V is requested, V1~V4 will be forced to 0xFF.
pointer action byte, V3, will be programmed to the selected default (microprocessor bit
SMPR_FXD_STFF_DEFLT
from 139 to 0 for VT2 mapping, the pointer generator sends out NDF-V indication with the correct pointer (0)
instead of the increment indication.
pointer action byte, V3, will be programmed to actual customer data. However, when decrementing from 0 to
139 for VT2 mapping, the pointer generator sends out NDF-V indication with the correct pointer (139) instead
of the decrement indication.
all mappings.
BIP-2
Table 560
Bit 2
00
01
10
11
below for error insertion modes.
REI-V
Bit 3
(Table
(Table
.
Table
67)), as well as the byte directly following V3. However, when incrementing
198) and automatically inserted.
199.)
RFI-V
Bit 4
No BIP-2 errors inserted.
Insert continuous BIP-2 errors.
Insert BIP-2 errors based on microprocessor register bit
SMPR_BER_INSRT
No BIP-2 errors inserted.
(Table
(Table
(continued)
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Table
198) to a 1. AIS-V consists of overwriting the entire VT,
Bit 5
199) will force BIP-2 errors for troubleshooting pur-
199), only a new BIP-2 and signal label is gener-
SIGNAL LABEL
Bit 6
(Table
Table
TMXF28155/51 Super Mapper
Action
65).
198)), all bits are simply passed
Bit 7
Table
Table 562, VT
559.
RDI-V
Bit 8
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