tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 410

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
18 SPE Mapper Functional Description
18.14 SPE Mapper Receive Direction Requirements
All monitoring functions supported by the SPE mapper in the receive direction are summarized here:
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The pointer interpreter transitions into the DEC state based on the following conditions:
The pointer interpreter transitions out of the DEC state based on the following conditions:
Pointer increments and decrements will be counted and presented to the microprocessor as follows:
LOP-TU3 (TU-3 path LOP) and AIS-TU3 (TU-3 path AIS) will be detected and reported to the microprocessor.
Both the LOP-TU3 and AIS-TU3 conditions will contribute to the AUTO AIS control signal from the SPE mapper
to the VT mapper. Any change in state of SPE_RLOP (
the microprocessor via SPE_RLOPD
is set (SPE_RLOPM/SPE_RAISM
The current TU-3 pointer value is stored in SPE_STORED_PTR[9:0] (
Loss of CLOCK and loss of sync monitors
J1 monitor
B3 BIP-8 check
C2 signal label monitor
F2 monitor
F3 monitor
N1 monitor
K3 monitor
AIS-P and RDI-P detect
REI-P detect
Signal degrade BER algorithm
Signal fail BER algorithm
Path overhead access channel (POAC) drop
Insertion of AIS-P
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the DEC state into
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC
— Following the number of consecutive invalid pointers (determined by the value programmed in
— Pointer increments and decrements will be monitored and counted internally.
— The internal and latched counts will be forced to 0x00 if device pin AUTO_AIS (AC6, AE6, and AD6) = 1 (from
— Latched counts, SPE_RPTR_INC[10:0]
— The internal counters will reset to 0x00 coincident with the end of a performance monitor interval.
— If SMPR_SAT_ROLLOVER = 1
— However, increment and decrement event indications should be ignored during LOP state.
correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions into the
DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming
H1 and H2 bytes the pointer interpreter transitions into the DEC state.
the NDF state.
the DEC state into the AIS-TU3 state.
DEC state into the NORM state.
state into the NORM state.
SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the DEC state into the LOP-TU3 state.
TMUX), bit SPE_RLOP = 1
coincident with the end of a performance monitor interval.
erwise, the counts will roll over.
(Table
(Table
(Table
(Table
148), or bit SPE_RAIS = 1
147)), SPE_RLOPD = 1 or SPE_RAISD = 1 will generate an interrupt.
67), the internal running counts will hold at their maximum value. Oth-
(Table
146) and SPE_RAISD
161) and SPE_RPTR_DEC[10:0]
(continued)
Table
148) or SPE_RAIS
(Table
(Table
Table
Table
148).
146). Unless the appropriate mask bit
149)), if 8 of the 10 I and D bits are
161).
(Table
(Table
148) will be reported to
161), will be updated
Agere Systems Inc.
May 2001