tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 370

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
In case of overflow, depending on the value programmed in the microprocessor interface register bit
SMPR_SAT_ROLLOVER
will either roll over or saturate at the maximum value until cleared.
17.5.5 J0 Monitor
J0 (section trace overhead) monitoring is done via register bits TMUX_J0MONMODE[2:0]
This J0 monitoring has six different monitoring modes, as follows:
17.5.6 Descrambler
A frame synchronous descrambler of length 127 and generating polynomial x
STS-3/STM-1 (or STS-1) signal except for the first row of overhead. The scrambler will be set to 1111111 on the
first byte following the last section overhead byte in the first row (i.e., after byte J0 for STS-1). The descrambler
operates in a byte-wide mode.
The frame descrambler can be enabled or disabled using register bit TMUX_RHSDSCR
370
TMUX_J0MONMODE[2:0] = 000: the TMUX latches the value of the J0 byte every frame for a total of
16 bytes into registers TMUX_J0DMON[16—1][7:0]; see
incoming J0 byte with the next expected value (the expected value is obtained by cycling through the previously
stored 16 received bytes in round-robin fashion) and, if different, setting the section trace identifier mismatch
state register bit, TMUX_RTIMS, see
delta and interrupt register bits TMUX_RTIMSD; see
Table 86 on page88
TMUX_J0MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for a 0x0A character to
indicate that the next byte is the first byte of the path trace message. The J0 byte message is continuously writ-
ten into TMUX_J0DMON[1—16][7:0] registers with the first byte residing at the first address. If any received byte
does not match the previously received byte for its location, then the state register bit, TMUX_RTIMS, is set. Any
change to RTIMS will be reported via delta and interrupt mask register bits TMUX_RTIMSD and
TMUX_RTIMSM.
TMUX_J0MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most
significant bit (MSB) set to one, which indicates that the next byte is the second byte of the message. The rest of
operation is the same as in SONET framing mode.
TMUX_J0MONMODE[2:0] = 011: a new J0 byte (TMUX_J0DMON[1][7:0]) will be detected after the number of
consecutive consistent occurrences of a new pattern in the J0 overhead byte as determined by the values in reg-
isters TMUX_CNTDJ0[3:0]; see
rupt mask registers TMUX_RTIMSD and TMUX_RTIMSM. The TMUX_RTIMSD delta bit in this mode indicates a
change in state for the TMUX_J0DMON[1][7:0] byte and the state register bit, TMUX_RTIMS, is not used.
TMUX_J0MONMODE[2:0] = 100: the user will program the 16 expected values of J0 in the SONET frame into
registers TMUX_EXPJ0DMON[1—16][7:0]; see
ing the 0x0A character, is written into the first location TMUX_J0DMON[1][7:0]. The TMUX compares the incom-
ing J0 sequence with the stored expected value and sets the state register bit, TMUX_RTIMS (
page
state) and TMUX_RTIMSM (interrupt mask).
TMUX_J0MONMODE[1:0] = 101: the user will program the 16 expected values of J0 in the SDH frame in regis-
ters TMUX_EXPJ0DMON[1—16][7:0]. The first byte of the message has the MSB set to 1. The TMUX compares
the incoming J0 sequence with the stored expected value, setting the state register bit, TMUX_RTIMS, if they are
different. Any change to TMUX_RTIMS will be reported via register bits TMUX_RTIMSD (delta state) and
TMUX_RTIMSM (interrupt mask).
TMUX_J0MONMODE[1:0] = 110 and 111 are currently undefined.
92), if they are different. Any change to TMUX_RTIMS is reported via register bits TMUX_RTIMSD (delta
.
(Table 67 SMPR_GCR, Global Control Register (RW) on page
Table 98 on page98
Table 91 on page92
(continued)
Table 131 on page
. Any changes to this byte are reported via delta and inter-
Table 82, starting on pag e79
Table 132 on page121
. Any change to TMUX_RTIMS will be reported via
121. The first expected byte, the byte follow-
7
+ x
6
. The TMUX compares the
+ 1 will descramble the entire
and TMUX_RTIMSM; see
(Table 93 on page94
68), the B1 error counter
(Table 95 on pag
Agere Systems Inc.
Table 91 on
May 2001
e95).
).