tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 595

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
TMXF28155/51 Super Mapper
May 2001
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
26 Applications
(continued)
26.11 Digital Jitter Attenuator
The digital jitter attenuator (DJA) contains 28 copies of the digital jitter attenuator block. These digital jitter attenua-
tor blocks can operate in two different modes, as a DS1 or as an E1 jitter attenuator.
In both modes, the digital jitter attenuator can be provisioned to always operate as a second-order PLL, or it can
switch to a act as a first-order PLL during VT pointer adjustments to help meet MTIE requirements. The period of
time in the first-order mode is provisionable. The PLL bandwidth is provisionable between 0.1 Hz and 0.5 Hz and
the damping factor for these bandwidths varies between 2 and 0.5 to accommodate a number of different system
constraints.
The block will also insert the proper AIS signal if the primary block AIS control input is active.
26.12 Test Pattern Generator
The test pattern generator and monitor (TPG and TPM) is a set of configurable test pattern generators and moni-
tors for local self-test, maintenance, and troubleshooting operations.
The TPG feeds one or more T1/E1/DS2 test signals (via data, clock, and FS or AIS signal paths) to the crosspoint
switch which can redistribute or broadcast these signals to any valid channel in the framer, external I/O, M13 map-
per, or VT mapper blocks. The TPG can also generate DS3 test signals.
Any channel arriving at the cross connect may be routed to the test monitor. The test monitors can automatically
detect/count bit errors in a pseudorandom test sequence, loss of frame, or loss of sync. The TPM can provide an
interrupt to the control system, or it can be operated in a polled mode.
Simultaneous testing of DS1, E1, DS2, and DS3 signals is supported (one channel each).
Supported test patterns are: pseudorandom bit sequence (PRBS15, PRBS20), alternating zeroes/ones, and an all-
ones pattern.
The test pattern can be transmitted either unframed or as the payload of a framed signal, as defined in ITU-T rec-
ommendation O.150.
Single bit-errors may be injected into any test pattern, under register control.
Agere Systems Inc.
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