tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 377

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
17 TMUX Functional Description
17.5.16 Path Monitoring Functions
The following sections describe the path monitoring functions. For STM-1 signals, the values corresponding to
STS-1 #1 are the relevant signals. For STS-3 input data, there are three versions of each path monitor, one corre-
sponding to each STS-1. The mode bits are applied to the monitors of all three STS-1s.
J1 Monitor. J1 (path trace) monitoring has six different monitoring modes controlled by TMUX_J1MONMODE[2:0]
(Table 95 on page95
Agere Systems Inc.
Pointer increments and decrements will be counted and presented to the microprocessor as follows:
The current pointer state is read from TMUX_RLOP[3—1] and TMUX_RPAIS[3—1]. Any changes in pointer con-
dition are read from the delta state bits TMUX_RLOPD[3—1] and TMUX_RPAISD[3—1]
ated interrupt mask bits are TMUX_RLOPM[3—1]
When the device is receiving a concatenated signal (STM-1(AU-3)), the receive concatenation mode register bit,
TMUX_RCONCATMODE
TMUX_CONCAT_STATE[3—2][1:0]
This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996
- Annex B.
TMUX_J1MONMODE[2:0] = 000: The TMUX latches the value of the J1 byte every frame for a total of 64 bytes
in TMUX_J1DMON[1—3][1—64][7:0]
the incoming J1 byte with the next expected value (the expected value is obtained by cycling through the previ-
ous stored 64 received bytes in round-robin fashion) and setting the path trace identifier state register bit(s),
TMUX_RTIMP[1—3]
TMUX_RTIMPD[1—3]
TMUX_J1MONMODE[2:0] = 001: This is the SONET framing mode. The hardware looks for the 0x0A character
to indicate that the next byte is the first byte of the path trace message. The J1 byte message is continuously
written into registers, TMUX_J1DMON[1—3][1—64][7:0], with the first byte residing at the first address. If any
received byte does not match the previously received byte for its location, then the state bit(s),
TMUX_RTIMP[1—3], is set. Any change to the path trace identifier is reported in TMUX_RTIMPD[1—3], with
interrupt masks bits, TMUX_RTIMPM[1—3].
TMUX_J1MONMODE[2:0] = 010: This is the SDH framing mode. The hardware looks for the byte with the MSB
set to one, which indicates that the next byte is the second byte of the message. The rest of operation is the
same as in SONET framing mode, except that there are 16 bytes instead of 64.
TMUX_J1MONMODE[2:0] = 011: A new J1 byte (TMUX_J1DMON[1][7:0]) will be detected after a number of
consecutive consistent occurrences of a new pattern (determined by the value in TMUX_CNTDJ1[3:0] (
on pag
the interrupt mask bits, TMUX_RTIMPM[1—3]. The delta bit(s) in this mode indicate a change in state for the
TMUX_J1DMON[1][7:0] byte, and the state bits, TMUX_RTIMP[1—3], are not used.
— Pointer increments and decrements will be monitored and counted internally.
— The internal and latched counts will be forced to clear (0x00) if TMUX_RLOP[3—1] = 1
— Upon the configured performance monitoring interval, raw counts are transferred to holding registers for
— Depending on the value of SMPR_SAT_ROLLOVER
— However, increment and decrement event indications should be ignored during LOP station.
or TMUX_RPAIS[3—1] = 1
pointer increments (TMUX_RPTR_INC[1—3][10:0]
TMUX_RPTR_DEC[1—3][10:0]
reset (to 0x00).
block, the internal running counts saturate at their maximum value or rollover.
e99)) in the J1 overhead byte. Any changes to this byte must be reported in TMUX_RTIMPD[1—3], with
). The J1 monitoring mode for all three STS-1s within an STS-3 signal is the same.
(Table 92 on page92
(Table
(Table 95 on page
83), with interrupt mask bits, TMUX_RTIMPM[1—3]
(Table
(Table
(Table 92 on page92
92), where [3—1] designates the tributary number.
(Table 137 on page122
130), allowing access by the microprocessor. The raw counters will
), if different. Any change to the path trace identifier is reported in
(continued)
95), must be set for the concatenation state machines (register bits
(Table 87 on page89
(Table 129 on page121
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table 67 on page68
)) on ports 2 and 3 to contribute to pointer evaluation.
,
Table
138, and
) and TMUX_RPAISM[3—1]
TMXF28155/51 Super Mapper
) in the microprocessor interface
Table
)) and decrements
(Table 87 on page89
139). The TMUX compares
(Table
(Table 92 on page
83). The associ-
(Table
Table 99
).
87).
92)
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