tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 589

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
TMXF28155/51 Super Mapper
May 2001
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
26 Applications
(continued)
26.2 High-Speed Line Interfaces and Clock and Data Recovery
In the receive direction, the Super Mapper accepts either a differential serial data signal at 155.52 Mbits/s
(STS-3/STM-1 mode) or a serial STS-1 clock and data at 51.84 MHz (STS-1 mode). For the STS-1 case, the input
is retimed with the input clock. A clock and data recovery circuit is used for the 155 Mbits/s case with the high-
speed transmit input clock as the clock reference. In the event that external clock and data recovery is provided,
this feature can be bypassed. The clock and date circuit can be used for recovering clock at 51 MHz, but a
155 MHz clock reference must still be supplied.
On the transmit side, in STS-3/STM-1 mode, the Super Mapper receives a differential 155.52 MHz transmit clock
and transmit frame sync signal and outputs a differential serial data signal. In STS-1 mode, it receives a
51.84 MHz transmit clock and frame sync signal and outputs serial data.
Loss of input clock or recovered clock is detected, as well as a loss-of-signal condition, by monitoring an external
signal pin or internally an all-zeros/ones pattern.
Built-in loopbacks at both high-speed interfaces provide maximum flexibility for maintenance testing.
26.2.1 Receive Direction
Terminating the transport overhead (TOH), the Super Mapper performs frame alignment (STS-3/STM-1 or STS-1),
B1 BIP-8 check, J0 monitoring, descrambling, F1 monitoring, B2 BIP-8 check, APS and K2 monitoring, AIS-L and
RDI-L detection, M1 REI-L detection, S1 sync status monitoring, and transport overhead access channel (RTOAC)
drop.
The states of the framer as well as all state changes are reported, and, if not masked, cause an interrupt.
The B1 and B2 parity check supports bit and block mode. The counters count up to one second worth of BIP
errors. They stay at their maximum value in case of overflow or rollover and should be read (and cleared) at least
once per second.
The J0 monitor supports nonframed, SONET-framed, and SDH-framed 16-byte sequences as well as single
J0 byte monitoring modes.
APS monitoring is performed on K1[7:0] and K2[7:3]. The value is stored and changes are reported. Bits [2:0] of
the K2 byte are monitored independently.
Line AIS (AIS-L/MS-AIS) and remote defect indication (RDI-L/MS-RDI) are monitored separately and changes are
reported. This information is also sent to the protection device for ADM applications.
The M1 monitor operates either in bit or block mode and allows accessing of the remote error indication
(REI-L/MS-REI) errored bit count.
The S1 byte can be monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits 7 to 4).
Continuous N times detection counters are implemented for these monitoring functions. All automatic receive mon-
itoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a
polled mode.
The receive transport overhead access channel (RTOAC) provides access to all of the line section overhead bytes.
Even or odd parity is calculated over all bytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and
an 8 kHz sync pulse. Alternatively, only the data communication channels D1—D3 or D4—D12 may transmit a
serial 192 kbits/s or a 576 kbits/s data stream.
26.2.2 Transmit Direction
In the transmit direction, the Super Mapper performs transmit transport overhead access channel (TTOAC) inser-
tion, sync status byte (S1) insertion, M0/M1—REI-L insertion, K1 and K2 insertion, AIS-L insertion, B2 calculation
and insertion, F1 byte insertion, B1 generation and error insertion, scrambler, J0 insert control, and A2 error inser-
tion.
Agere Systems Inc.
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