tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 472

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
20 M13/M23 MUX/DeMUX Block Functional Description
Frame Status and Error Reporting. The M13 provides information on the earliest frame still in the FIFO through
status register M13_RHDLC_STATUS_R
The status register has 1 bit to indicate whether or not the closing flag (or an abort byte) for the current frame has
been received, 1 bit to indicate if the current frame is corrupted, 5 bits to indicate the size of the current frame mod-
ulo-32, and 1 bit to indicate whether or not there are less than 32 bytes of the earliest frame left in the FIFO.
There are
been aborted (M13_RDL_ABORT = 1
(M13_RDL_FCS_ERR = 1
a multiple of 8 (M13_RDL_NOT_BYTE = 1
FIFO (M13_RDL_OVFL = 1
whether or not the closing flag (or an abort byte) for the current frame has been received.
The size of the current frame modulo-128 (including FCS bytes only if M13_RDL_FCS = 0
by register M13_RDL_FRAME_SIZE_R
DS3 Performance Monitors. For performance monitoring purposes, there are a number of error counters in the
M13. All of these internal counters are comprised of a running error counter and a hold register that presents stable
results to the microprocessor. The counts in all of the running counters are latched to the hold registers and the
running counters cleared with the configured internal performance monitor reset signal.
The latched results are then held to be read by the microprocessor. All of the internal counters have the ability to
store more than the maximum possible count in a one second interval for a bit error rate of 10
formance monitor reset occurs at least once every second, no counts will be lost. In case this doesn’t happen, all of
the running counters will either hold their maximum value or roll over to zero, depending on the control signal input
SMPR_SAT_ROLLOVER
Within the M23 demultiplexer, there are four performance monitoring counters. M13_DS3_FERR_CNT[11:0]
(Table
(Table
mode only, M13_DS3_CPERR_CNT[13:0]
indicating an error, and M13_DS3_FEBE_CNT[13:0]
cation for each DS3 frame with at least one FEBE bit equal to zero).
20.11.4 M12 Demultiplexers
Each M12 demultiplexer outputs either 4 DS1 signals from the DS2 frame as specified in GR-499-CORE (when
M13_DS1_E1Ny = 1
G.747 (when M13_DS1_E1Ny = 0). In the DS1 mode, the demultiplexed second and fourth channels are inverted
before being sent to the output selectors when M13_DEMUXCH2_4_INVy = 1
Each M12 DeMUX can be programmed independently to receive DS2 signal either from M23 deMUX (when
M13_M12DMX_MODEy[1:0] = 00
M13_M12DMX_MODEy[1:0] = 01). In the latter case, an input DS2 clock XC_DS2DMXCLKy is also required.
When M13_M12DMX_MODEy[1:0] = 10/11, the M12 demultiplexer is idle and the outputs are held low.
The DS2 signal is monitored for AIS, which is declared (M13_DS2_AIS_DETy = 1
input is 0 for fewer than five clock cycles in each of two consecutive 840 clock periods, and cleared if there are
more than 4 zeros in each of two consecutive 840-bit periods (G.775).
20.11.5 DS1 Mode
Framer. The M12 demultiplexers determine if the input signal contains valid DS2 framing. This is done in two
stages by first finding a bit position that matches the M-subframe alignment pattern (F bits), and then locating the M
frame alignment signal (M bits). After a matching F-bit sequence is found, in-frame is declared (M13_DS2_OOFy =
0
time is 2.5 ms in the presence of a bit error rate of 10
472
(Table
289) increments each time an error is detected in either an F bit or M bit, and M13_DS3_PERR_CNT[13:0]
292) increments if at least one of the P bits disagrees with the parity of the previous frame. In the C-bit parity
240)) when correct M bits are received for three consecutive M frames. The maximum average reframe
four
ways in which the M13 can identify that the current frame has been corrupted. The frame may have
(Table
(Table
(Table
263)), or three E1 signals from the DS2 format specified in ITU-T Recommendation
(Table
67).
253)), the number of bits between opening and closing flags may not have been
(Table
253)). Also, there is a separate bit M13_RDL_FLAG
(Table
(Table
272)) or direct DS2 input XC_DS2DMXDATAy (when
(Table
(Table
(Table
253)), it may have failed the CRC check
255).
256).
253)), or it may have been overwritten before being read from the
291) counts frames with at least two of the three C-bit parity bits
(Table
–3
.
290) accumulates FEBE error indications (1 error indi-
(continued)
(Table
(Table
272).
(Table
242)) if the demultiplexer
(Table
–3
253) to indicate
. As long as the per-
Agere Systems Inc.
287)) is indicated
May 2001