tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 8

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Contents
3 Pin Information ..................................................................................................................................................... 8
Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)........................................................................................... 9
Figure 3. Protection Switch..................................................................................................................................... 16
Figure 4. DS1/E1 to DXC Block Diagram ............................................................................................................... 23
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order ....................................................................... 9
Table 2. Pin Assignments for 456-Pin PBGA by Signal Name .............................................................................. 12
Table 3. High-speed I/O Pin Descriptions ............................................................................................................. 15
Table 4. Protection Switch I/O Pin Description ...................................................................................................... 16
Table 5. Telecom Bus (Low-speed I/O) Pin Description ........................................................................................ 17
Table 6. TOAC and POAC .................................................................................................................................... 19
Table 7. Miscellaneous Signals ............................................................................................................................. 20
Table 8. DS3 Port .................................................................................................................................................. 21
Table 9. DS3 Port, C-Bit, and Datalink Access ..................................................................................................... 22
Table 10. M13 Multiplexer/Demultiplexer Receive Section ................................................................................... 22
Table 11. Low-Order Path Overhead Access Channel ......................................................................................... 23
Table 12. Multifunction System Interface Transmit Path Direction ........................................................................ 24
Table 13. Framer PLL ............................................................................................................................................ 27
Table 14. Microprocessor Interfaces ..................................................................................................................... 28
Table 15. General Purpose Interface .................................................................................................................... 29
Table 16. Test Pins ................................................................................................................................................ 30
Table 17. CDR Power ............................................................................................................................................ 30
Table 18. LVDS Control Pins ................................................................................................................................. 30
8
3.1 456-Pin PBGA Pin Diagram ........................................................................................................................... 9
3.2 Pin Assignments ............................................................................................................................................ 9
3.3 Pin Descriptions ........................................................................................................................................... 15
3.4 Outline Diagram ........................................................................................................................................... 32
3.3.1 High-speed I/O Pin Descriptions ........................................................................................................ 15
3.3.2 Protection Switch I/O Pin Description ................................................................................................ 16
3.3.3 Telecom Bus (Low-speed I/O) Pin Description .................................................................................. 16
3.3.4 TOAC and POAC ............................................................................................................................... 19
3.3.5 Miscellaneous Signals ........................................................................................................................ 20
3.3.6 DS3 Port ............................................................................................................................................. 20
3.3.7 M13 Multiplexer/Demultiplexer Receive Section ................................................................................ 22
3.3.8 Low-Order Path Overhead Access Channel ...................................................................................... 23
3.3.9 Framer PLL ........................................................................................................................................ 27
3.3.10 Test Pins .......................................................................................................................................... 30
3.4.1 456-Pin PBGA .................................................................................................................................... 32
Interface Specifications
Table of Contents
List of Figures
List of Tables
Agere Systems Inc.
May 2001
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