tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 60

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics
Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications
(See Figure 17 on page 59
Notes:
1 DSN can be asserted up to 20 ns (1 clk at 50 MHz) previous to CSN.
2 ADDR can be asserted up to 60 ns (3 clk at 50 MHz) into cycle from ASDN.
3 DTN fall is variable depending on the block selected for access and may be longer than typical maximum specified.
4 Leading edges of ADSN and DSN determine the falling edge of DTN.
5 Rising edge of ADSN determines the rising edge of DTN.
6 Data toggle 20 ns (1 clk at 50 MHz) previous to CSN.
Note: Specifications are valid for 50 MHz MPCLK with MPMODE = 0. Address strobe (ADSN) and chip select
5.13 General Purpose Interface Timing
Table 55. Input Timing Specifications
60
t
Symbol
ADSRDTR
t
t
t
t
t
t
t
t
CSFDSF
t
CSFDTR
DSFDTF
CSRDT3
t
ADSRD3
AVADSF
t
ADSRAI
DSNRAI
DTVDV
AVDSF
AICSR
(CSN) may be connected and driven from the same source. In this configuration, the setup and hold times
for ADSN must be satisfied.
SCAN_MODE
Input Name
IC3STATEN
SCAN_EN
PMRST
TRSTN
TMSN
RSTN
IDDQ
TDI
CSN Fall to DSN Fall
ADDR Invalid to CSN Rise
ADDR Valid to ADSN Fall
ADSN Rise to ADDR Invalid
ADDR Valid to DSN Fall
DSN Rise to ADDR Invalid
CSN Fall to DTN Rise
DSN Fall to DTN Fall
ADSN Rise to DTN Rise
CSN Rise to DTN 3-state
DTN Valid to DATA Valid
ADSN Rise to DATA 3-state
for the timing diagram.)
Parameter
Reference CLK
(continued)
TCLK
TCLK
NA
NA
NA
NA
NA
NA
NA
Miscellaneous Signals
JTAG Signals
Min Setup Time (t
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
15.0 ns
15.0 ns
Min Interval (ns)
100
20
20
10
20
0
0
0
0
0
0
0
1
6
S)
Min Hold Time (t
Max Interval (ns)
Agere Systems Inc.
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
2.0 ns
2.0 ns
280
60
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May 2001
3, 4
5
2
H)