tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 24

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Table 12. Multifunction System Interface Transmit Path Direction
24
J3, J4, K4, L4,
C11, C10, A9,
B11, B10, B9,
M3, M4, N2,
M2, N1, P4,
C6, C5, C4,
G3, G4, H2,
D8, C8, A7,
B6, D5, A4,
C2, D2, E2,
F4, G2, H1,
B8, D7, C7,
A3, H5, F5,
D3, E3, F3,
C3, J5, B2,
J1, K3, L3,
D12, C12,
C13, A12,
P2, R4
D13
B13
Pin
P3
LINERXDATA[28:1]
LINERXCLK[28:1]
LINERXDATA29
LINERXCLK29
Symbol
(continued)
Type
—
—
—
—
Pull down
Pull down
Pull down
Pull down
I/O
I/O
I/O
I
I
Line Receive Data (28:1). Configurable inputs to the
internal cross connect. The use depends on the appli-
cation. Generally, these inputs are used for the received
positive-rail or single-rail DS1/E1 line data input. If oper-
ating in dual rail mode, the negative rail will be expected
on LINERXSYNC(28:1). Using dual rail mode implies
that the internal B8ZS or HDB3 decoders are enabled,
and line code violations can be detected and counted
inside the Super Mapper.
These data inputs may be assigned, using the cross
connect block, to the DS1 or E1 inputs on the VT map-
per, M13 or DS1/E1 framers. It is also possible to use
the inputs for DS2 data, in which case they may be
assigned to the M23 multiplexer inputs.
Receive Data 29. Configurable input to the internal
cross connect. May be used as an additional line
receive data input, for a protection channel. Other pos-
sible uses are as follows:
Global transmit line clock input. Externally supplied
1.544 MHz or 2.048 MHz low jitter clock phase-locked
to the TDM system clock. Used for transmit line clock on
the DS1/E1 framers. This is not normally used, because
the DS1/E1 framer has a PLL which can generate a
1.544 MHz clock from the TDM system clock (CHI
clock). This applies in PSB and CHI modes.
Receive data input. If NSMI mode is used, this will be a
51.84 Mbits/s serial data input.
Receive Clock (28:1). Configurable inputs/outputs to
the internal cross connect. Typically a line clock associ-
ated with the corresponding LINERXDATA input. It can
therefore be running at DS1, E1 or DS2 rate. The cross
connect is used to assign these inputs to the VT map-
per, M13 or DS1/E1 framers.
Receive Clock 29. May be used as additional receive
clock input for a DS1/E1 protection channel. Also has
special use as a master clock. In CHI mode, it is the
receive clock input (2.048 MHz, 4.096 MHz, 8.192 MHz,
or 16.384 MHz). In PSB mode, it is the receive clock
input (19.44 MHz). In NSMI mode, it is the receive clock
output. (51.84 MHz).
Description
Agere Systems Inc.
May 2001