cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet
cl-pd6833
Related parts for cl-pd6833
cl-pd6833 Summary of contents
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... BUS Version 0.3 PCI-to-CardBus Host Adapter OVERVIEW The CL-PD6833 easily interfaces with the 8- and 16-bit R2 PC Cards and the 32-bit CardBus PC Cards the third device to be developed in Cirrus Logic’s family of CardBus controllers. The CL-PD6833 gives system designers of portable, notebook, and handheld computers the most integrated solution for their needs ...
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... OVERVIEW (cont.) The CL-PD6833 is compliant with the latest PC 97 and PC 98 design guidelines. The CL-PD6833 is also compliant with PCI 2.1, PCI 2.2 draft, PC Card Standard (March 1997), ExCA , and JEIDA 4.2 standards. Like the CL-PD6834, the register set of the CL-PD6833 is a superset of the Intel 365-SL, the CL-PD672X, and the CL-PD6832 register sets ...
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... PCI/Way DMA .........................................................................................................................34 3.1.6 Power Management ................................................................................................................34 3.1.7 Socket Power Management Features .....................................................................................35 3.1.8 Bus Sizing ...............................................................................................................................37 3.1.9 Programmable PC Card Timing ..............................................................................................37 3.1.10 ATA Mode Operation ...............................................................................................................37 3.1.11 PC Card Sensing ....................................................................................................................37 3.2 Upgrading from the CL-PD6832 to the CL-PD6833.............................................................................38 3.2.1 Added Registers......................................................................................................................39 3.3 Host Access to Registers .....................................................................................................................42 3.4 Power-On Setup...................................................................................................................................44 4. REGISTER DESCRIPTION CONVENTIONS.......................................................................45 5. PCI CONFIGURATION REGISTERS....................................................................................47 5.1 Vendor ID and Device ID......................................................................................................................48 5 ...
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... Gen Map 0–6 End Address Low (Memory)...........................................................................127 10.2.4 Gen Map 0–6 End Address High (Memory)..........................................................................128 10.2.5 Gen Map 0–6 Offset Address Low (Memory)........................................................................129 10.2.6 Gen Map 0–6 Offset Address High (Memory).......................................................................130 4 TABLE OF CONTENTS CL-PD6833 PCI-to-CardBus Host Adapter June 1998 ADVANCE DATA BOOK v0.3 ...
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... CL-PD6833 PCI-to-CardBus Host Adapter 11. EXTENSION REGISTERS .................................................................................................131 11.1 Misc Control 1 ....................................................................................................................................132 11.2 FIFO Control ......................................................................................................................................134 11.3 Misc Control 2 ....................................................................................................................................136 11.4 Chip Information.................................................................................................................................137 11.5 ATA Control ........................................................................................................................................138 11.6 Extended Index ..................................................................................................................................140 11.7 Extended Data ...................................................................................................................................141 11.7.1 Extension Control 1...............................................................................................................142 11.7.2 Gen Map 0–6 Upper Address (Memory) ...............................................................................143 11.7.3 Pin Multiplex Control 0 Register — PME_CXT .....................................................................144 11.7.4 Pin Multiplex Control 1 Register — ...
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... PCI Bus Timing .....................................................................................................................186 15.3.2 System Interrupt Timing ........................................................................................................191 15.3.3 PC Card (PCMCIA) Bus Timing Calculations........................................................................192 15.3.4 PC Card (PCMCIA) Bus Timing ............................................................................................193 16. PACKAGE SPECIFICATIONS............................................................................................ 199 17. ORDERING INFORMATION .............................................................................................. 201 A. PIN LISTINGS..................................................................................................................... 203 INDEX.................................................................................................................................. 211 6 TABLE OF CONTENTS CL-PD6833 PCI-to-CardBus Host Adapter June 1998 ADVANCE DATA BOOK v0.3 ...
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... In this document, the names of the CL-PD6833 internal registers are boldface. For example, Chip Revision and Power Control are register names. The names of bit fields are written with initial uppercase letters. For example, Card Power On and Battery Voltage Detect are bit fi ...
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... The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘n/c’ indi- cates a pin that is a ‘no connect’. In addition, an uppercase X is used within numbers to indicate digits ignored by the CL-PD6833 within the current context. For example, ‘ 101XX01’ binary number with bits 3:2 ignored. ...
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... CL-PD6833 PCI-to-CardBus Host Adapter 2. PIN INFORMATION The CL-PD6833 is packaged in a 208-pin MQFP (formerly PQFP) or LQFP (formerly VQFP) component package. The CL-PD6833 interface pins can be divided into four groups: PCI bus interface pins PC Card socket interface pins (two sets) Power control and general interface pins ...
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... Figure 2-1. Pin Diagram for PC Card 16 (R2) 10 PIN INFORMATION PCI-to-CardBus Host Adapter +5V A_SOCKET_VCC CL-PD6833 208-Pin MQFP or LQFP PCI_VCC ‡ the end of the pin name indicates signals that are used ADVANCE DATA BOOK v0.3 CL-PD6833 A_VS2 104 103 A_A6 102 A_A25 101 RING_GND 100 A_A7 99 A_A24 ...
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... INTB#/RI_OUT*/PME# 204 SOUT#/ISLD/IRQSER 205 SIN#/ISDAT/GPIO2/LED2 206 RST# 207 CLKRUN# 208 Figure 2-2. Pin Diagram for PC Card 32 (CardBus) June 1998 ADVANCE DATA BOOK v0.3 +5V A_SOCKET_VCC CL-PD6833 208-Pin MQFP or LQFP PCI_VCC A_CVS2 104 103 A_CAD20 102 A_CAD19 101 RING_GND 100 A_CAD18 99 ...
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... AD0 is pin 56 The quantity (Qty.) column indicates the number of pins used (per socket where applicable). The I/O-type code (I/O) column indicates the input and output configurations of the pins on the CL-PD6833. The possible types are defined below. The power-type code (Pwr.) column indicates the output drive power source for an output pin or the pull-up power source for an input pin on the CL-PD6833. The possible types are defi ...
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... Device Select: When actively driven, this signal indi- cates that it has decoded its own PCI address as the target of the current access input, DEVSEL# indicates to the CL-PD6833 whether any device on the bus has been selected. PERR# Parity Error: The CL-PD6833 drives this output active (low detects a data parity error during a write phase ...
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... It ensures even parity across AD[31:0] and C/BE[3:0]#. PCI_CLK PCI Clock: This input provides timing for all transac- tions on the PCI bus to and from the CL-PD6833. All PCI bus interface signals described in this table (Table 2-1), except RST#, INTA#, and INTB# are sampled on the rising edge of PCI_CLK ...
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... During I/O cycles for non-DMA transfers, this signal is active (low). During ATA mode, this signal is always inactive. For DMA cycles on the CL-PD6833 to a DMA- capable card, -REG is inactive during I/O cycles to indicate DACK to the PC Card 16. In CardBus mode, this pin is the command and byte enable 3 ...
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... When a socket is configured as an ATA drive interface, socket interface pin functions change. See 16 PIN INFORMATION (cont.) Pin Number 2 Socket A Socket 153, 149, 77, 73 CL-PD6833 PCI-to-CardBus Host Adapter Qty. I/O Pwr. Drive I/O 168 I/O 166 I/O 164 ...
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... In CardBus mode, this pin is the CardBus address/data bit 13. -IOWR/ I/O Write: This output goes active (low) for CAD15 I/O writes from the CL-PD6833 to the socket. In CardBus mode, this pin is the CardBus address/data bit 15 differentiate the sockets in the pin diagram, all socket-specific pins have either prepended to the pin names indi- cated ...
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... In CardBus mode, this pin is the CardBus SERR# signal. -CD[2:1]/ Card Detect: These inputs indicate to the CCD[2:1]# CL-PD6833 that a card is in the socket. They are internally pulled high to the volt- age of the +5V power pin. In CardBus mode, these inputs are used in conjunction with CVS[2:1] to detect the presence and type of card ...
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... In CardBus mode, this pin is the CardBus address/data bit 10. -CE1/ Card Enable: This pin is driven low by the CCBE0# CL-PD6833 during card access cycles to control byte/word card access. -CE1 enables even-numbered address bytes, and -CE2 enables odd-numbered address bytes. When configured for 8-bit cards, ...
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... BVD1 (battery-dead status) input. In I/O Card Interface mode, this input is the -STSCHG input, which indicates to the CL-PD6833 that the card’s internal status has changed. If bit 7 of the Interrupt and General Control register is set to ‘1’, this pin serves as the ring indicate input for wakeup-on-ring system power manage- ment support ...
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... Table 2-2) operate at the voltage applied to these pins, independent of the voltage applied to other CL-PD6833 pin groups differentiate the sockets in the pin diagram, all socket-specific pins have either prepended to the pin names indi- cated. For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets. ...
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... SMBus mode of opera- tion and requires an external pull-up. This pin is used to detect power-up during reset (see Section 3.2 on page 22 PIN INFORMATION (cont.) Description Pin Number for more 38). CL-PD6833 PCI-to-CardBus Host Adapter Qty. I/O Pwr. 133 1 I/O 1 132 1 I – ...
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... CL-PD6833 PCI-to-CardBus Host Adapter Table 2-3. Power Control and General Interface Pins Pin Name SLATCH/ Serial Latch / System Management Bus ‡ SMBCLK Clock: This pin serves as output pin SLATCH when used with the serial interface of Texas Instruments’ TPS2206AIDF socket power control chip, and serves as bidirectional pin SMBCLK when used with Intel’ ...
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... This pin provides power to the core circuitry of the CL-PD6833. This pin must be connected to the 3.3-V supply. CORE_GND All the CL-PD6833 ground lines should be con- nected to system ground. RING_GND All the CL-PD6833 ground lines should be con- nected to system ground. 24 PIN INFORMATION Description Pin Number 14, 28, 44, 57, ...
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... CardBus functions of the CL-PD6833 are compatible with the PC Card Standard. Under software control, the CL-PD6833 uses the VS1, VS2, CD1, and CD2 pins in the manner described by the PC Card Standard to identify and power up the PC Card. The PC Card type (R2 or CardBus) determines its voltage requirements ...
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... CL-PD6833 R2 Windowing Capabilities For full compatibility with existing software and to ensure compatibility with future R2 memory card and R2 multifunction I/O cards, the CL-PD6833 provides seven programmable general-purpose windows per socket. These windows default at reset to two I/O windows and five memory windows. Any one of the seven windows can be programmed to respond on the PCI primary bus as either a memory or I/O window and to issue either a memory or I/O cycle to the R2-compatible PC Card. For example, in the case of a non-’ ...
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... The timing of accesses (setup/command/recovery) can be set by either of two timing register sets: Timer Set 0 or Timer Set 1. CAUTION: The windows of the CL-PD6833 should never be allowed to overlap with each other or the other devices in the system. This would cause signal collisions and result in erratic behavior. ...
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... End Address Registers System I/O Map Start Address Registers System I/O Map uses ‘0’ for Upper Address Registers *NOTE: The CL-PD6833 only decodes the first 64 Kbytes Figure 3-2. R2 I/O-to-I/O Window Organization Page 255 System Memory Map End Address Registers System Memory Map Start Address Registers ...
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... Multimedia Enable bit (bit 0 of the Misc Control 1 register at index 16h or memory offset 816h) is set to a ‘1’. The CL-PD6833 has a Multimedia Arm bit (bit 7 of the Misc Control 3 register at I/O index 2Fh, Extended Index 25h, or memory offset 925h), which works as an overriding control bit. Until the Multimedia Arm bit is set, the Multimedia Enable bit does not tristate the address pins as previously described ...
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... COM1, the software would expect the modem to generate interrupts on the IRQ4 line sure all interrupts are routed as expected, the CL-PD6833 can steer the interrupt from the PC Card to one of the four PCI-bus-defined interrupts or to one of several standard PC interrupts. The CL-PD6833 supports four interrupt schemes: PCI Interrupt, Intel’ ...
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... Battery warning indicator (BVD2) change on a memory-type card Ready (RDY) status change on a memory-type card Any interrupt from either class of interrupts can be steered by the CL-PD6833 to any interrupt output. This is useful because IRQ-type interrupts in PC-compatible systems are not generally shared by hardware. Therefore, each device in the system using IRQ-type interrupts must have a unique interrupt line. Addi- tionally, many software applications assume that certain I/O devices use specifi ...
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... In this mode, pin 203 functions as INTA#, and pin 204 functions as INTB#/RI_OUT*. Refer to application note Interrupt Signalling Modes for the CL-PD6730 and CL-PD6832 (AN-PD8) . This is the only mode that supports pulse mode interrupts. The CL-PD6833 contains unique logic that allows ISA-style, IRQ-type interrupts to be shared under software control. This is accomplished by programming the CL-PD6833 to alternately pulse and then tristate the desired interrupt pin, which is programmed as an IRQ-type output ...
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... The number of interrupts supported depends on the SIC configuration. Figure 3-9. PC/PCI Serial Interrupt Signalling Mode The SIN# pin on the CL-PD6833 is the serial interrupt input line from other devices in the interrupt loop, and the SOUT# pin is the serial interrupt output line containing the logical ‘AND’ of the interrupt level in the CL-PD6833, along with SIN# interrupts ...
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... Suspend mode, the CL-PD6833 tristates all its outputs except the REQ# signal, which is driven high. During HW Suspend mode, the PCI bus signals to the CL-PD6833 can be turned off. However, the RST# signal on the PCI bus must always be held high. An inactive state of the RST# signal ensures that the internal state of the CL-PD6833 is maintained during the power-down modes ...
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... Card power interface switch, which uses a three-pin interface: SCLK, SDATA, and SLATCH (refer to Figure 3-10). The pin SCLK is connected to the 10–100-kHz (usually 32-kHz) clock typically available on the system. This serves as a reference clock for the CL-PD6833 and as a clock to the TPS2206AIDF. The data is serially transferred over SDATA and the latch signal is SLATCH. SDATA/SMBDATA (131) SLATCH/SMBCLK (130) Figure 3-10 ...
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... I C bus. The serial data is available on the SMBDATA pin and the serial clock is on the SMBCLK pin. The SCLK pin is used as a reference clock for the CL-PD6833. The Maxim MAX1601 dual-channel PC Card V /V power-switching network supports the SMBus protocol. The PCI bus reset signal can ...
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... There are two sets of timing registers, Timer Set 0 and Timer Set 1, which can be selected on a per-window basis for both I/O and memory windows. 3.1.10 ATA Mode Operation The CL-PD6833 supports direct connection to ATA hard drives when in PC Card 16 mode. ATA drives use an interface very similar to the IDE interface found on many popular portable computers. 3.1.11 PC Card Sensing The CL-PD6833 provides sensing capabilities for all types of cards and voltages compliant with the PC Card Specifi ...
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... CL-PD6832 or the CL-PD6833 in the same footprint. Table 3-7 depicts the essence of upgrading. The register bits in Context). They do not get reset or initialized if PME enable is true when the CL-PD6833 changes power states from through a software PCI bus segment reset. Table 3-7. ...
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... The following registers have been added to the PCI Configuration space. NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. 3.2.1.1 Pin Multiplex Control 0 Register — PME_CXT ...
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... Bit 7 Bit INTRODUCTION TO THE CL-PD6833 Pin Function a INTA# or LED1* GPIO1 Do not program this value. Do not program this value. Pin Function SIN#, ISDAT, or LED2* with control of pin characteristics per the CL-PD6832 bits. GPIO2 Do not program this value. ...
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... INTB# or RI_OUT*, using existing CL-PD6832 select bits. Do not program this value. PME# as defined by PCI specification (PCI power management add-on specification). Do not program this value. PCI Memory Address: 915h Bit 2 Bit 1 Bit 0 INTB#/ INTB#/ RI_OUT*/ RI_OUT*/ PME# PME# Sel 1 Sel 0 R/W:0 R/W:0 INTRODUCTION TO THE CL-PD6833 41 ...
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... CL-PD6833 memory base address offset 10h in the configuration space. To access registers in I/O-Mapped mode, program offset 44h in the configuration space accordingly. In I/O- Mapped mode, the CL-PD6833 registers are accessed through an 8-bit indexing mechanism. An Index reg- ister scheme allows a large number of internal registers to be accessed by the CPU using only two I/O addresses ...
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... CL-PD6833 PCI-to-CardBus Host Adapter The CL-PD6833 has Extension registers that add to the functionality of the 82365SL-compatible register set. Within the Extension registers is an Extended Index register and Extended Data register that provide access to more registers. The registers accessed through Extended Index and Extended Data are thus double-indexed ...
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... MOV Eax, 090A1206h MOV ES: [BX], eax 3.4 Power-On Setup Following RST#-activated reset, the CL-PD6833 must be configured by host initialization or BIOS software. The application of the RST# signal on power-up causes initialization of all the CL-PD6833 register bits and fields to their reset values. 44 INTRODUCTION TO THE CL-PD6833 CL-PD6833 ...
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... These read-only bits are forced to either ‘0’ or ‘1’ at reset and cannot be changed. Compatibility Bit These bits have no function on the CL-PD6833, but are included for compatibility with the 82365SL register set. PCI/Way These bits provide the programming model for the PCI/Way DMA support. ...
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... Status Indicates one of two types of bits: either read-only bits used by the CL-PD6833 to report information to the system or bits set by the CL-PD6833 in response to an event that can also be cleared by the system. The system cannot directly cause a Status bit to become ‘1’. Value Indicates that the bit or fi ...
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... PCI CONFIGURATION REGISTERS The CL-PD6833 has two PCI Configuration register sets. Each of these register sets corresponds to a socket. The second socket is the second function and starts at 100h. These register sets occupy config- uration offsets 00h–4Fh. The register sets vary only in the function number (see PCI Bus Specification , Rev ...
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... Bits 31:16 — Device ID This read-only field is the device identification assigned to this device by Cirrus Logic. This field always reads back 1113h for the CL-PD6833. (Revision number identification for the CL-PD6833 part itself is indicated by the Revision ID field in the Revision ID and Class Code register at confi ...
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... Bit 0 — PCI I/O Space Enable This bit does not affect R2 I/O space. If this bit is ‘0’ for both Sockets A and B, any reads or writes to the I/O registers of the CL-PD6833 are 0 ignored. If this bit is a ‘1’, I/O accesses to the registers or CardBus card are carried out. For confi ...
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... Bit 24 — Master Data Parity Error Reported This bit is set when a parity error is generated or detected, bit 6 of this register is set, and the CL-PD6833 is acting as a bus master. To clear this bit, software must write a ‘1’ to it. Bits 26:25 — DEVSEL# Timing This field always reads back ‘01’, identifying the CL-PD6833 as a medium-speed device. ...
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... Bit 8 of this register must be set before system errors can be reported, and bit 6 must be set to allow address parity errors to be detected. The CL-PD6833 only asserts SERR# if address parity errors occur. To clear this bit, software must write a ‘1’ to it. ...
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... This read-only value depends on the revision level of the CL-PD6833. Bits 7:0 — Revision ID (‘11100001’) This read-only field identifies the revision level of the CL-PD6833. It reflects the value of bits 5:0 of the Chip Information register (index 1Fh). Bits 7 and 6 always read back a ‘1’. ...
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... Bits 15:8 — Latency Timer 7:0 This field programs the master latency time-out value. If the full byte is available, the latency timer programs in increments of one PCI clock (PCI_CLK), but because bits 10:8 on the CL-PD6833 are read-only and must be programmed to 0h, master latency time-out values are programmable in increments of eight PCI clocks. Bits 23:16 — ...
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... This bit indicates that the Controller registers are not prefetchable. Bits 31:4 — Controller Memory Base Address This field specifies the memory-mapped register space of the CL-PD6833. The Operation registers can be accessed through this window only after these bits are set to a non-zero value. ...
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... CL-PD6833 PCI-to-CardBus Host Adapter 5.6 CardBus Status Register Name: CardBus Status Offset: 14h Bit 31 Bit 30 Address/Data Received Byte 3 Parity Error System Error CardBus Detected (SERR#) Status (high) RC:0 RC:0 Bit 23 Bit 22 Byte 2 CardBus Status (low) Bit 15 Bit 14 Byte 1 Bit 7 Bit 6 Byte 0 NOTE: The CardBus (Secondary) Status bytes are similar to the Status bytes in the Command and Status regis- ter, but contain information relating to the CardBus. Bit 30 is defi ...
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... Interrupt Line, Interrupt Pin, and Bridge Control register must be set to allow address parity errors to be detected. The CL-PD6833 only asserts SERR# if address parity errors occur. To clear this bit, software must write a ‘1’ to it. ...
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... CL-PD6833 PCI-to-CardBus Host Adapter 5.7 PCI Bus Number, CardBus Number, Subordinate Bus Number, and CardBus Latency Timer Register Name: PCI Bus Number, CardBus Number, Subordinate Bus Number, and CardBus Latency Timer Offset: 18h Bit 31 Bit 30 Byte 3 CardBus Latency Timer 7:3 CardBus Latency ...
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... PCI CONFIGURATION REGISTERS Bit 29 Bit 28 Memory Base 31:24 R/W:11111111 Bit 21 Bit 20 Memory Base 23:16 R/W:11111111 Bit 13 Bit 12 R/W:1111 Bit 5 Bit 4 Memory Base 7:0 R:00000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Bit 27 Bit 26 Bit 25 Bit 19 Bit 18 Bit 17 Bit 11 Bit 10 Bit 9 Memory Base 11:8 R:0000 Bit 3 Bit 2 Bit 1 ADVANCE DATA BOOK v0 ...
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... CL-PD6833 PCI-to-CardBus Host Adapter 5.9 Memory Limit 0–1 Register Name: Memory Limit 0–1 Offset: 20h, 28h Bit 31 Bit 30 Byte 3 Bit 23 Bit 22 Byte 2 Bit 15 Bit 14 Byte 1 Memory Limit 15:12 Bit 7 Bit 6 Byte 0 NOTE: Memory Base 0–1 and Memory Limit 0–1 are enabled by bit 1 of the Command and Status register (memory offset 04h) ...
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... Bits 1:0 — I/O Space Indicator 1:0 These bits are an extension to the I/O Base register and always read back ‘00’. The value ‘00’ indicates that the CL-PD6833 supports 16-bit PCI I/O address decoding. As described in the PCI-to-CardBus Register description specification , this means I/O access intended for CardBus cards require PCI address bits 31: ‘ ...
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... CL-PD6833 PCI-to-CardBus Host Adapter 5.11 I/O Limit 0–1 Register Name: I/O Limit 0–1 Offset: 30h, 38h Bit 31 Bit 30 Byte 3 Bit 23 Bit 22 Byte 2 Bit 15 Bit 14 Byte 1 Bit 7 Bit 6 Byte 0 Bits 1:0 — Reserved These bits are reserved and always read back ‘00’. Bits 15:2 — I/O Limit 15:2 These bits defi ...
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... This register is used by software to communicate the routing of the interrupts (INTA# for Socket A and INTB# for Socket B). Bits 15:8 — Interrupt Pin These read-only registers indicate that the CL-PD6833 requires one interrupt line per function (Socket A and Socket B) and that these lines are INTA# and INTB#. Bit 16 — CardBus Parity Error Response Enable This bit determines the response to parity errors on the CardBus interface ...
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... Interrupt Pin register (memory offset 3Dh): INTA# for Socket A and INTB# for Socket B. If the CL-PD6833 is programmed for Ring Indicate, then INTB# is used for ring out and INTA# is used for both Sockets A and B, that is, INTB# is not available for function interrupt routing. ...
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... Operating with write posting disabled inhibits system performance. 0 Write posting is disabled. 1 Write posting is enabled. Bits 31:27 — Reserved 64 PCI CONFIGURATION REGISTERS CL-PD6833 PCI-to-CardBus Host Adapter June 1998 ADVANCE DATA BOOK v0.3 ...
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... CL-PD6833 PCI-to-CardBus Host Adapter 5.13 Subsystem Vendor ID and Subsystem Device ID Register Name: Subsystem Vendor ID and Subsystem Device ID Offset: 40h Bit 31 Bit 30 Byte 3 Subsystem Device ID (high) Bit 23 Bit 22 Byte 2 Subsystem Device ID (low) Bit 15 Bit 14 Byte 1 Subsystem Vendor ID (high) Bit 7 Bit 6 Byte 0 Subsystem ...
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... Bits 31:2 — Controller I/O Base Address This field specifies the I/O-mapped register space of the CL-PD6833. The Operation registers can be accessed through this window only after these bits are set to a non-zero value. The allowable range is anywhere in the I/O map. For legacy software, this register should be set to ‘ ...
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... Bits 15:8 — Next Item Pointer This register indicates that this section is the last of the capabilities structures. Bits 18:16 — PCI Power Management Revision The value ‘001’ indicates that the CL-PD6833 complies with version 1.0 of the PCI Power Management Interface Specification . Bits 31:19 — Power Management Capabilities ...
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... Bits 7:2 — Reserved Bit 8 — PME Enable (PME_En) This bit enables the wake-up function of the CL-PD6833. When this bit is set, wake-ups are signalled on the PME pin. When this bit is reset, no wake-ups are issued. Bits 12:9 — Data Select These bits read back ‘0’s to indicate that data selection is not supported. ...
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... CL-PD6833 PCI-to-CardBus Host Adapter Bit 15— PME Status This bit indicates that an event has occurred that, if the PME Enable bit is set, would cause PME to be signalled. Writing a ‘1’ to this bit clears it to ‘0’, and writing ‘0’ to this bit has no effect. ...
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... Non-Legacy Extended Addressing R/W:0000 Size of DMA Transfer at the PC Card 16 (R2) Socket 8-bit transfer at the PC Card 16-bit transfers at the PC Card 16-bit transfers at the PC Card 16-bit transfers at the PC Card CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Bit 27 Bit 26 Bit 25 Bit 19 Bit 18 Bit 17 ...
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... For software compatibility with earlier CL-PD67XX PC Card host adapters, many of the CL-PD6833 internal registers are accessible at the I/O address pair 03E0h and 03E1h by setting a register index at one address, and then accessing the 8-bit register data at the next address. June 1998 ADVANCE DATA BOOK v0.3 ...
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... I/O address pair and index range so that it appears as a particular socket number out of the eight possible socket number locations found in older ISA-based PC Card host adapters. Refer to Chapter 7 for information about the organization of the Index register. Bits 31:3 — Reserved 72 PCI CONFIGURATION REGISTERS CL-PD6833 PCI-to-CardBus Host Adapter June 1998 ADVANCE DATA BOOK v0.3 ...
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... Bit 1 — Management Enable This bit is used to control the routing of management interrupts to the ISA IRQ or PCI INT pin. This is used only when the CL-PD6833 is programmed for non-PCI style interrupts. Management interrupts are routed to the INT pin indicated by the Interrupt Pin register (memory offset 0 3Dh): INTA# for Socket A and INTB# for Socket B ...
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... This bit determines the CL-PD6833 action when the socket’s PCI function power state. This bit is part of the PME_CXT, a set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. ...
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... NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. The Status Event register indicates when a change in socket status occurs. These bits do not indicate what the change is, only that a change occurred. Software must read the Present State register for cur- rent status. Bits 3:0 can be cleared by writing a ‘ ...
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... This bit indicates a change has occurred in the corresponding Card Detect bit. Bit 3 — Power Cycle This bit defaults to ‘0’ set to ‘1’ by the CL-PD6833 to indicate that the device has completed powering up or powering down. The Present State register (memory offset 008h) should be read to determine that the voltage requested is actually applied ...
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... Bit 2 — CCD2 Changed When set, this bit enables an interrupt when the CL-PD6833 detects change. Bit 3— Power Cycle Complete When set, this bit causes the CL-PD6833 to generate an interrupt 256 cycles of the PCI clock after powering up a socket. Bits 31:4 — Reserved June 1998 ADVANCE DATA BOOK v0 ...
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... This bit reflects the current status of the CSTSCHG/WAKEUP pin on the CardBus interface. Bit 1 — CCD1 This bit provides for detection Card insertion/removal/presence also used by the CL-PD6833, in conjunction with CVS1, to determine the card type (PC Card 16 vs. PC Card 32 reflection of the CCD1 pin. Bit 2 — CCD2 This bit provides for detection Card insertion/removal/presence ...
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... This bit indicates that a card was removed while the interface was active. Data may be lost. Any data in the CL-PD6833 data buffers is lost when this event occurs. This bit is set to ‘0’ by RST#. This bit allows software to fail in a graceful manner chooses to, when this occurs. ...
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... They provide software the ability to force various status and event bits in the CL-PD6833. This gives software the ability to test and restore status. Writing ‘1’ bit in this register sets the corresponding bit in the Status Event register and/or the Present State register. Bits 3:0 generate Management Interrupt if the correct Mask bit is set. Bit 0 — ...
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... This bit causes the 3.3-V Card bit in the Present State register to be set. Writes to this bit disables the CL-PD6833’s ability to power up the socket. To change the voltage of a card, after forcing this bit, the CL-PD6833 must either receive a RST# or retest the card’s supported voltages. The latter can be accomplished by forcing the CV Test bit (bit 14 in this register) ...
Page 82
... R/W:0 NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from software PCI Bus Segment reset. The Socket Control register provides control of the socket’ ‘0’ by RST# and power removed from the socket. This register is write-protected by writes to bits 13:10 of the Event Force register, and not write-protected on completion of the decoding sequence of the CD1, CD2, VS1, and VS2 lines or completion of CV test ...
Page 83
... CC These bits are used to control the power to the PC Card using external control logic. The CL-PD6833 determines the voltages that can be applied by decoding the CD and VS signals according to the CardBus specification , which are reflected in the Present State register. The settings in the Present State register that determine the voltages available in the system determine the V options ...
Page 84
... CARDBUS REGISTERS PCI-to-CardBus Host Adapter Notes ADVANCE DATA BOOK v0.3 CL-PD6833 June 1998 ...
Page 85
... PCI-to-CardBus Host Adapter 7. OPERATION REGISTERS In I/O mode, the CL-PD6833 internal Device Control, Window Mapping, Extension, and Timing regis- ters are accessed through a pair of Operation registers — an Index register and a Data register. The Index register is accessed at the address that is programmed in the I/O Base Address register, and ...
Page 86
... ADVANCE DATA BOOK v0.3 CL-PD6833 PCI-to-CardBus Host Adapter Chapter Page 91 92 Chapter 8, 94 “DEVICE 96 CONTROL REGISTERS” 101 105 125 126 127 128 ...
Page 87
... CL-PD6833 PCI-to-CardBus Host Adapter Table 7-1. Index Registers Register Name Gen Map 2 Start Address Low Gen Map 2 Start Address High Gen Map 2 End Address Low Gen Map 2 End Address High Gen Map 2 Offset Address Low Gen Map 2 Offset Address High ATA Control ...
Page 88
... Extended index 36h Extended index 37h Extended index 38h Extended index 39h Extended index 3Ah Extended index 3Bh 2Fh 30h 31h 32h 33h 34h 35h CL-PD6833 PCI-to-CardBus Host Adapter Memory Chapter – 900h Reserved Reserved 903h Reserved 840h 841h 842h ...
Page 89
... CL-PD6833 PCI-to-CardBus Host Adapter Table 7-1. Index Registers Register Name Gen Map 5 Offset Address Low Gen Map 5 Offset Address High Gen Map 6 Offset Address Low Gen Map 6 Offset Address High Setup Timing 0 Command Timing 0 Recovery Timing 0 Setup Timing 1 Command Timing 1 Recovery Timing 1 ...
Page 90
... The Data register is accessed at I/O Base Address + 1. This register indicates the contents of the register at the Socket/Register Index selected by the Index register. 90 OPERATION REGISTERS Bit Bit Bit Data CL-PD6833 PCI-to-CardBus Host Adapter Register Per: chip Register Compatibility Type: 365 Bit Bit Bit June 1998 ...
Page 91
... These bits always read ‘0’s. Bits 7:6 — Interface ID Bit 7 Bit These bits identify the type of interface this controller supports. The CL-PD6833 supports both memory and I/O interface PC Cards. June 1998 ADVANCE DATA BOOK v0.3 I/O Index Memory Offset 00h 800h 01h 801h 02h 802h ...
Page 92
... Intr. Request On a R:1 R:0 a Bit 7 always reads ‘1’ on the CL-PD6833. b Bit 5 indicates the value of the RDY/IREQ# pin (see the source of interrupt request either from socket I/O card mode, this bit always indicates the inverted state of the RDY/BSY INTR# pin. c Bit 4 indicates the value of the WP/IOIS16# pin (see ...
Page 93
... CL-PD6833 PCI-to-CardBus Host Adapter Bit 4 — Write Protect 0 Card is not write-protected. 1 Card is write-protected. In Memory Card Interface mode, this bit indicates the state of the WP/IOIS16# pin (see on the card. This bit is not valid in I/O Card Interface mode. Bit 5 — Ready / Busy* / Interrupt Request Status 0 Card is not ready ...
Page 94
... NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. This register is write-protected by writes to the Event Force register. The register is not write protected when a CV test completes ...
Page 95
... CL-PD6833 PCI-to-CardBus Host Adapter Bits 1:0 — Power PP Bit 1 Bit This state exists under conditions where V These bits control the power to the V Bits 3:2 — Compatibility Bits Bit 4 — V Power CC 0 Power is not applied to the card. ...
Page 96
... Card Reset* Card is I/O Enable R/W:0 R/W:0 NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. Bits 3:0 — PC Card IRQ Selection Bit 3 Bit ...
Page 97
... CL-PD6833 PCI-to-CardBus Host Adapter Bit 4 — Compatibility Bit Bit 5 — Card is I/O 0 Sets Memory Card Interface mode. The card socket is configured to support memory-only-type cards. All dual-function socket interface pins are defined to perform memory-only-type interface functions. 1 Sets I/O Card Interface mode. The card socket is configured to support combined I/O-and-memory- type cards. All dual-function socket interface pins are defi ...
Page 98
... NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. This register indicates the source of a management interrupt generated by the CL-PD6833. ...
Page 99
... NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. This register controls which status changes cause management interrupts. They also control the pin loca- tion where the management interrupts appear. Bit 0 — ...
Page 100
... IRQ7 0 0 IRQ8 for PCI/Way operation, Reserved for others 0 1 IRQ9 1 0 IRQ10 1 1 IRQ11 0 0 IRQ12 0 1 IRQ13 for PCI/Way operation, Reserved for others 1 0 IRQ14 1 1 IRQ15 CL-PD6833 PCI-to-CardBus Host Adapter Interrupt Pin June 1998 ADVANCE DATA BOOK v0.3 ...
Page 101
... CL-PD6833 PCI-to-CardBus Host Adapter 8.7 Mapping Enable Register Name: Mapping Enable I/O Index: 06h Memory Offset: 806h Bit 7 Bit 6 I/O Map 1 I/O Map 0 Compatibility Enable Enable R/W:0 R/W:0 Bit 0 — Memory Map 0 Enable 0 Memory Window Mapping registers for Memory Window 0 disabled. 1 Memory Window Mapping registers for Memory Window 0 enabled. ...
Page 102
... I/O Window Mapping registers for I/O Window 1 enabled. When this bit is ‘1’, the I/O Window Mapping registers for I/O Window 1 are enabled and the con- troller responds to I/O accesses in the I/O space defined by those registers. 102 DEVICE CONTROL REGISTERS CL-PD6833 PCI-to-CardBus Host Adapter June 1998 ADVANCE DATA BOOK v0.3 ...
Page 103
... CL-PD6833 PCI-to-CardBus Host Adapter 9. WINDOW MAPPING REGISTERS Table 9-1. Window Mapping Registers Quick Reference Register Name I/O Window Mapping Registers I/O Window Control System I/O Map 0–1 Start Address Low System I/O Map 0–1 Start Address High System I/O Map 0–1 End Address Low System I/O Map 0–1 End Address High Card I/O Map 0– ...
Page 104
... Don’t Care Memory Memory Set to ‘1’ I/O Reset to ‘0’ I/O Memory Reset to ‘0’ Memory Memory Set to ‘1’ Memory CL-PD6833 PCI-to-CardBus Host Adapter Window Configuration I/O Standard Mapping Standard Mapping I/O General Mapping General Mapping General Mapping I/O General Mapping June 1998 ...
Page 105
... CL-PD6833 PCI-to-CardBus Host Adapter 9.1 I/O Window Mapping Registers 9.1.1 I/O Window Control Register Name: I/O Window Control I/O Index: 07h Memory Offset: 807h Bit 7 Bit 6 Timing Compatibility Auto-Size I/O Register Bit Window 1 Select 1 R/W:0 R/W:0 R/W:0 Bit 0 — I/O Window 0 Size 0 8-bit data path to I/O Window 0. 1 16-bit data path to I/O Window 0. ...
Page 106
... Accesses made with timing specified in Timer Set 0. 1 Accesses made with timing specified in Timer Set 1. This bit determines the access timing specification for I/O Window 1. 106 WINDOW MAPPING REGISTERS CL-PD6833 PCI-to-CardBus Host Adapter June 1998 ADVANCE DATA BOOK v0.3 ...
Page 107
... CL-PD6833 PCI-to-CardBus Host Adapter 9.1.2 System I/O Map 0–1 Start Address Low Register Name: System I/O Map 0–1 Start Address Low I/O Index: 08h, 0Ch Memory Offset: 808h, 80Ch Bit 7 Bit 6 There are two separate System I/O Map Start Address Low registers, each with identical fields. These ...
Page 108
... WINDOW MAPPING REGISTERS Bit 5 Bit 4 Bit 3 End Address 7:0 R/W:00000000 Bit 5 Bit 4 Bit 3 End Address 15:8 R/W:00000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 Bit 0 Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 Bit 0 June 1998 ADVANCE DATA BOOK v0 ...
Page 109
... Bits 7:1 — Offset Address 7:1 This register contains the least-significant byte of the quantity that is added to the system I/O address to determine where in the PC Card’s I/O map the I/O access occurs. The CL-PD6833 internally defines bit 0 of offset address as ‘0’. The most-significant byte is located in the Card I/O Map 0–1 Offset Address High register. ...
Page 110
... The most-significant four bits are located in the System Memory Map 0–4 Start Address High register. 110 WINDOW MAPPING REGISTERS 9.2.1). Bit 5 Bit 4 Bit 3 Start Address 19:12 R/W:00000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 Bit 0 June 1998 ADVANCE DATA BOOK v0.3 ...
Page 111
... CL-PD6833 PCI-to-CardBus Host Adapter 9.2.2 System Memory Map 0–4 Start Address High Register Name: System Memory Map 0–4 Start Address High I/O Index: 11h, 19h, 21h, 29h, 31h Memory Offset: 811h, 819h, 821h, 829h, 831h Bit 7 Bit 6 Compatibility Window Data Bit Size ...
Page 112
... The most-significant four bits are located in the System Memory Map 0–4 End Address High register. 112 WINDOW MAPPING REGISTERS Bit 5 Bit 4 Bit 3 End Address 19:12 R/W:00000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 Bit 0 June 1998 ADVANCE DATA BOOK v0.3 ...
Page 113
... CL-PD6833 PCI-to-CardBus Host Adapter 9.2.4 System Memory Map 0–4 End Address High Register Name: System Memory Map 0–4 End Address High I/O Index: 13h, 1Bh, 23h, 2Bh, 33h Memory Offset: 813h, 81Bh, 823h, 82Bh, 833h Bit 7 Bit 6 Card Timer Select R/W:00 There are five separate System Memory Map End Address High registers, each with identical fields. ...
Page 114
... The most-significant six bits are located in the Card Memory Map 0–4 Offset Address High register. 114 WINDOW MAPPING REGISTERS Bit 5 Bit 4 Bit 3 Offset Address 19:12 R/W:00000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 Bit 0 June 1998 ADVANCE DATA BOOK v0.3 ...
Page 115
... CL-PD6833 PCI-to-CardBus Host Adapter 9.2.6 Card Memory Map 0–4 Offset Address High Register Name: Card Memory Map 0–4 Offset Address High I/O Index: 15h, 1Dh, 25h, 2Dh, 35h Memory Offset: 815h, 81Dh, 825h, 82Dh, 835h Bit 7 Bit 6 Write Protect REG Setting R/W:0 R/W:0 There are five separate Card Memory Map Offset Address High registers, each with identical fields. ...
Page 116
... WINDOW MAPPING REGISTERS PCI-to-CardBus Host Adapter Notes ADVANCE DATA BOOK v0.3 CL-PD6833 June 1998 ...
Page 117
... CL-PD6833 PCI-to-CardBus Host Adapter 10. GENERAL WINDOW MAPPING REGISTERS Table 10-1. General Window Mapping Registers Quick Reference Register Name General Mapping Registers for I/O Mode Gen Map 0–6 Start Address Low (I/O) Gen Map 0–6 Start Address High (I/O) Gen Map 0–6 End Address Low (I/O) Gen Map 0– ...
Page 118
... Map 6. Memory Windows 0–4 correspond to Gen Map 0–4. CAUTION: Be sure that the I/O windows do not map to the I/O Base Address register programmed at offset 44h in the configuration space. 118 GENERAL WINDOW MAPPING REGISTERS CL-PD6833 PCI-to-CardBus Host Adapter page 101). June 1998 ADVANCE DATA BOOK v0.3 ...
Page 119
... CL-PD6833 PCI-to-CardBus Host Adapter 10.1 General Mapping Registers for I/O Mode 10.1.1 Gen Map 0–6 Start Address Low Register Name: Gen Map 0–6 Start Address Low (I/O) I/O Index: 08h, 0Ch, 10h, 18h, 20h, 28h, 30h Memory Offset: 808h, 80Ch, 810h, 818h, 820h, 828h, 830h ...
Page 120
... Gen Map 6 Start Address High Gen Map 0 Start Address High Gen Map 1 Start Address High Gen Map 2 Start Address High Gen Map 3 Start Address High Gen Map 4 Start Address High CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 ...
Page 121
... CL-PD6833 PCI-to-CardBus Host Adapter 10.1.3 Gen Map 0–6 End Address Low (I/O) Register Name: Gen Map 0–6 End Address Low (I/O) I/O Index: 0Ah, 0Eh, 12h, 1Ah, 22h, 2Ah, 32h Memory Offset: 80Ah, 80Eh, 812h, 81Ah, 822h, 82Ah, 832h Bit 7 Bit 6 There are seven separate Gen Map End Address Low registers, each with identical fields. These ...
Page 122
... Gen Map 6 End Address High Gen Map 0 End Address High Gen Map 1 End Address High Gen Map 2 End Address High Gen Map 3 End Address High Gen Map 4 End Address High CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 ...
Page 123
... CL-PD6833 PCI-to-CardBus Host Adapter 10.1.5 Gen Map 0–6 Offset Address Low (I/O) Register Name: Gen Map 0–6 Offset Address Low (I/O) I/O Index: 14h, 1Ch, 24h, 2Ch, 34h, 36h, 38h Memory Offset: 814h, 81Ch, 824h, 82Ch, 834h, 836h, 838h Bit 7 Bit 6 a This bit must be programmed to ‘0’ for I/O offset. ...
Page 124
... Gen Map 1 Offset Address High Gen Map 2 Offset Address High Gen Map 3 Offset Address High Gen Map 4 Offset Address High Gen Map 5 Offset Address High Gen Map 6 Offset Address High CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: ext. Bit 2 Bit 1 ...
Page 125
... CL-PD6833 PCI-to-CardBus Host Adapter 10.2 General Mapping Register for Memory Mode 10.2.1 Gen Map 0–6 Start Address Low (Memory) Register Name: Gen Map 0–6 Start Address Low (Memory) I/O Index: 08h, 0Ch, 10h, 18h, 20h, 28h, 30h Memory Offset: 808h, 80Ch, 810h, 818h, 820h, 828h, 830h ...
Page 126
... Gen Map 6 Start Address High Gen Map 0 Start Address High Gen Map 1 Start Address High Gen Map 2 Start Address High Gen Map 3 Start Address High Gen Map 4 Start Address High CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 ...
Page 127
... CL-PD6833 PCI-to-CardBus Host Adapter 10.2.3 Gen Map 0–6 End Address Low (Memory) Register Name: Gen Map 0–6 End Address Low (Memory) I/O Index: 0Ah, 0Eh, 12h, 1Ah, 22h, 2Ah, 32h Memory Offset: 80Ah, 80Eh, 812h, 81Ah, 822h, 82Ah, 832h Bit 7 Bit 6 There are seven separate Gen Map End Address Low registers, each with identical fields. These ...
Page 128
... Gen Map 6 End Address High Gen Map 0 End Address High Gen Map 1 End Address High Gen Map 2 End Address High Gen Map 3 End Address High Gen Map 4 End Address High CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 ...
Page 129
... CL-PD6833 PCI-to-CardBus Host Adapter 10.2.5 Gen Map 0–6 Offset Address Low (Memory) Register Name: Gen Map 0–6 Offset Address Low (Memory) I/O Index: 14h, 1Ch, 24h, 2Ch, 34h, 36h, 38h Memory Offset: 814h, 81Ch, 824h, 82Ch, 834h, 836h, 838h Bit 7 Bit 6 There are seven separate Gen Map Offset Address Low registers, each with identical fields. These ...
Page 130
... Gen Map 6 Offset Address High page 15) is not active for accesses made through this window. page 15) is active for accesses made through this page 123). CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 R/W:000000 Default Operation ...
Page 131
... CL-PD6833 PCI-to-CardBus Host Adapter 11. EXTENSION REGISTERS Table 11-1. Extension Registers Quick Reference Register Name Misc Control 1 FIFO Control Misc Control 2 Chip Information ATA Control Extended Index Extended Data Extension Control 1 Gen Map 0–6 Upper Address (Memory) Pin Multiplex Control 0 Register — PME_CXT Pin Multiplex Control 1 Register — ...
Page 132
... Power Control register. This bit is part of the PME_CXT (PME Context), a set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. 132 EXTENSION REGISTERS (cont ...
Page 133
... CL-PD6833 PCI-to-CardBus Host Adapter Bit 2 — Pulse Management Interrupt 0 Interrupts are passed to the IRQ[XX] pin as level-sensitive. 1 When an interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown in allows for interrupt sharing. This bit is valid only in External Hardware Interrupt Signalling mode. This bit selects Level or Pulse mode operation of the IRQ[XX] pin ...
Page 134
... Bit 5 Bit 4 Bit 3 CardBus-to- I/O Reserved PCI FIFO Disable R/W:0 R/W:0 R/W:0 Memory Prefetch Prefetching is enabled. Prefetching by CardBus master of PCI memory addresses is disabled. CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: ext. Bit 2 Bit 1 Bit 0 Enable CardBus-to- Memory Prefetch Disable CardBus Posting R/W:0 R/W:00 June 1998 ADVANCE DATA BOOK v0 ...
Page 135
... CL-PD6833 PCI-to-CardBus Host Adapter Bit 5 — Disable I/O Posting This bit disables posting of I/O writes when host PCI is bus master and is performing I/O writes to CardBus or R2 cards. 0 Posting of I/O writes is enabled. 1 Posting of I/O writes is disabled. When this bit is set, I/O writes from the PCI bus Card do not post to the FIFO, but are issued directly to the PC Card. Bit 6 — ...
Page 136
... BVD1/STSCHG#/RI# pin. Bit 5 of index 03h must be set to ‘1’ for RI to work. 136 EXTENSION REGISTERS Bit 5 Bit 4 Bit 3 Reserved R/W:0000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: chip Register Compatibility Type: ext. Bit 2 Bit 1 Bit 0 June 1998 ADVANCE DATA BOOK v0.3 ...
Page 137
... Identification Socket R:11 Bit 0 — DMA Capable A ‘1’ in this bit indicates that the CL-PD6833 is capable of DMA. Bits 4:1 — CL-PD6833 Revision Level This field is ‘1111’, indicating to software that Device Identification registers described in Section 11.9 on page 159 PC Card controllers, if bits 4:1 of the register at Memory Offset 81Fh read back ‘0h’, the chip information is contained in bits 3:0 of the register at Memory Offset 934h. Bit 5 — ...
Page 138
... PC Card socket pin definitions in ATA mode. This bit is part of the PME_CXT (PME Context), a set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. Bit 1 — Speaker is LED Input 0 Normal operation ...
Page 139
... CL-PD6833 PCI-to-CardBus Host Adapter Bit 6 — A24/M/S* In ATA mode, the value in this bit is applied to the ATA A24 pin and is vendor-specific. Certain ATA drive vendor-specific performance enhancements beyond the PCMCIA 2.1 standard can be controlled through use of this bit. This bit has no hardware control function when not in ATA mode. ...
Page 140
... CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: ext. Bit 2 Bit 1 – – – 903h – 840h 841h 842h 843h 844h – ...
Page 141
... CL-PD6833 PCI-to-CardBus Host Adapter Table 11-2. Extended Index Registers Register Name at Index 2Fh Misc Control 3 SMB Power Control Address Gen Map 0 Extra Control Gen Map 1 Extra Control Gen Map 2 Extra Control Gen Map 3 Extra Control Gen Map 4 Extra Control Gen Map 5 Extra Control ...
Page 142
... Bit 142 EXTENSION REGISTERS Bit 5 Bit 4 Bit 3 Reserved R/W:0 R/W:0 R/W:0 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: ext. Bit 2 Bit 1 V LED Activity Reserved Enable R/W:0 R/W:0 Pin Used DREQ Disabled INPACK# WP/IOIS16 BVD2/SPKR# ADVANCE DATA BOOK v0.3 ...
Page 143
... CL-PD6833 PCI-to-CardBus Host Adapter 11.7.2 Gen Map 0–6 Upper Address (Memory) Register Name: Gen Map 0–6 Upper Address (Memory) I/O Index: 2Fh Extended Index: 05h–09h, 20h, 21h Memory Offset: 840h, 841h, 842h, 843h, 844h, 845h, 846h Bit 7 Bit 6 These bits are used in comparing PCI Address bits 31:24 for each memory window (0–6). These bits are used in conjunction with the Window Type Select, Gen Map 0– ...
Page 144
... R/W:0 NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. Bits 1:0 — INTA#/LED1*/GPIO1 Select 1:0 These bits select the function of pin 203. ...
Page 145
... June 1998 ADVANCE DATA BOOK v0.3 Pin Function SPKR_OUT* with control of pin characteristics per the CL-PD6833. GPIO3 Do not program this value. Do not program this value. Pin Function LED_OUT* or HW_SUSP* with control of pin characteristics per the CL-PD6833 GPIO4 PME# as defined by the PCI specification (PCI power management add-on specifi ...
Page 146
... Bit 6 NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. Bits 1:0 — INTB#/RI_OUT*/ PME# Select 1:0 These bits select the function of pin 204. ...
Page 147
... CL-PD6833 PCI-to-CardBus Host Adapter 11.7.5 GPIO Output Control Register Name: GPIO Output Control I/O Index: 2Fh Extended Index: 18h Memory Offset: 918h Bit 7 Bit 6 Reserved R/W:0 R/W:0 R/W:0 Bits 3:0 — GPIO[4:1] Output Control When these bits are ‘0’, the corresponding GPIO pin is put into the high-impedance state. Setting these bits causes the corresponding GPIO Output Data bit to be driven onto the corresponding GPIO pin ...
Page 148
... Bits 7:4 — Reserved 148 EXTENSION REGISTERS Bit 5 Bit 4 Bit 3 GPIO4 Output Data R/W:0 Bit 5 Bit 4 Bit 3 GPIO4 Input Data R:1 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: chip Register Compatibility Type: ext. Bit 2 Bit 1 GPIO3 Output GPIO2 Output GPIO1 Output Data Data R/W:0 R/W:0 R/W:0 Register Per: chip Register Compatibility Type: ext ...
Page 149
... Byte 2 (low) Bit 15 Bit 14 Byte 1 (high) Bit 7 Bit 6 Byte 0 (low) This register is read-only in the current version of the CL-PD6833. 11.8.1 PCI Space Control Register Name: PCI Space Control I/O Index: 2Fh Extended Index: 22h Memory Offset: 922h Bit 7 Bit 6 Gen Map 6 Gen Map 5 Reserved ...
Page 150
... PC Card PC Card Type Type R/W:0 R/W:0 R/W:0 Bit 5 Bit 4 Bit 3 Gen Map 4 Gen Map 3 Type Type R/W:0 R/W:0 R/W:0 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: ext Bit 2 Bit 1 Bit 0 Gen Map 2 Gen Map 1 Gen Map 0 PC Card PC Card PC Card Type Type Type R/W:0 ...
Page 151
... SPKR_OUT* (128) from NOTE: Bits 3:0 are part of the PME_CXT (PME Context), a set of bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. Table 11-3. Interrupt Signalling Power-on Settings ...
Page 152
... When this bit is ‘0’, the TI’s TPS2206 serial interface protocol is enabled. This interface uses three pins: SCLK, SDATA, and SLATCH. SCLK is the reference clock to the CL-PD6833. The power control data is sent to TI’s TPS2206 over the SDATA pin and latch signal over the SLATCH pin. ...
Page 153
... R/W:0 R/W:1 NOTE: PME_CXT (PME Context set of register bits that do not get reset or initialized if PME Enable is true when the CL-PD6833 changes power states from through a software PCI Bus Segment reset. Bits 1:0 — Reserved Bits 7:2 — SMBus Socket Power Control Address A[6:1] This register contains the most-significant six bits of the SMBus (system management bus) slave address for the socket power-control device. The SMBus specifi ...
Page 154
... This bit determines the access timing specification for Gen Map I/O Window. Bits 7:4 — Reserved 154 EXTENSION REGISTERS Bit 5 Bit 4 Bit 3 Extra Timing Register Select R/W:0 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: ext. Bit 2 Bit 1 Bit 0 Extra Extra Reserved Auto-Size I/O I/O Window ...
Page 155
... CL-PD6833 PCI-to-CardBus Host Adapter 11.8.7 Gen Map 0–6 Extra Control (Memory) When the Window Type Select register bit corresponding to a general map register is set (and that window is configured in PC Card space control as Memory), this register is used to program the Memory behavior to the PC Card socket. When the Window Type Select register bit is reset, this register is ignored. When the Window Type Select register bit is set and the PC Card Space Control register bit is set to ‘ ...
Page 156
... R:0 R:0 This register indicates the source of a management interrupt generated by the CL-PD6833. NOTE: The corresponding bit in the Management Interrupt Configuration register must be set to ‘1’ to enable each specific status change detection. This register can only be cleared after accessing register 804h, and writing a ‘ ...
Page 157
... CL-PD6833 PCI-to-CardBus Host Adapter Bit 3 — Card Detect Change 0 A transition on neither the CD1# nor the CD2# pin has occurred since this register was last read transition on either the CD1# or the CD2# pin or both has occurred. This bit is set to ‘1’ when a change has occurred on the CD1# or CD2# pin. This bit is reset to a ‘ ...
Page 158
... EXTENSION REGISTERS Bit 5 Bit 4 Bit 3 Reserved R:0000000 Bit 5 Bit 4 Bit 3 3.3-V 5-V Socket W:1 W:1 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: ext. Bit 2 Bit 1 Bit 0 Dual LED Enable R/W:0 page 151. Register Per: socket Register Compatibility Type: ext. Bit 2 Bit 1 ...
Page 159
... CL-PD6833 PCI-to-CardBus Host Adapter 11.9 Device Identification and Implementation Scheme There are four-byte-wide registers with read-only device information, and four-byte-wide read/write regis- ters that contain specific system implementation information. Determining This Register Exists If bits 4:1 of the Chip Information register (memory offset 81Fh) read back ‘0h’, the chip information is contained in bits 3:0 of the Mask Revision register (memory offset 934h) ...
Page 160
... Bits 11:8 — Product Code These bits indicate the product code of the device within its family. Product Codes — CL-PD6833 family 0h CL-PD6833 PCI/CardBus controller, dual isolated sockets, 208-pin MQFP or LQFP. 2h–Fh Reserved for future use for the CL-PD683X devices. Bits 15:12 — Family Code A value of ‘ ...
Page 161
... A value of ‘0’ indicates that the CL-PD6833 does not support driving an external IDE drive. Bit 19 — Slave DMA A ‘1’ at this bit indicates that the CL-PD6833 can act as a DMA slave. The Slave DMA Wired bit (bit 2 of the Device Implementation Byte A register; see is wired to allow this feature to be used. Bit 20 — ...
Page 162
... RFU (ZV) Definitions R:0 Bit 24 — CardBus Capable A ‘1’ in this bit indicates that the CL-PD6833 is capable of supporting PC Card 32 (CardBus) cards. Bit 25 — LOCK# Support A ‘1’ indicates that the CL-PD6833 is capable of supporting operations involving the LOCK# signal. Note that bit 25 of the Device Implementation Byte D register must be referenced to determine whether LOCK supported signal in the system implementation. Bit 26 — ...
Page 163
... CL-PD6833 PCI-to-CardBus Host Adapter 11.9.5 Device Implementation Byte A Register Name: Device Implementation Byte A I/O Index: 38h Memory Offset: 938h Bit 7 Bit 6 Hardware GPSTB B RI_OUT Wired Suspend Wired Wired R/W:0 R/W:0 R/W:0 All bits of this byte are read/write. Device reset defaults are specific to each device. A BIOS write to this byte before bringing of socket services sets these bits to refl ...
Page 164
... Bit 15 — RFU (reserved for future use) 164 EXTENSION REGISTERS Bit 13 Bit 12 Bit 11 VPP 12 V X-V Capable Available R/W:0 R/W:1 R/W:0 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: chip Register Compatibility Type: ext. Bit 10 Bit 9 5.0-V V 3.3 Y-V Capable Capable Capable R/W:0 R/W ...
Page 165
... CL-PD6833 PCI-to-CardBus Host Adapter 11.9.7 Device Implementation Byte C Register Name: Device Implementation Byte C I/O Index: 3Ah Memory Offset: 93Ah Bit 23 Bit 22 RFU RFU (ZV) R/W:0 R/W:0 Bit 16 — LED Wired A value of ‘1’ indicates that a single activity socket LED is available for both sockets. A value of ‘0’ ...
Page 166
... LOCK#. Bits 29:26 — RFU (reserved for future use) Bit 30 — Clk Option Wired A value of ‘1’ indicates that an external clock is available to the CL-PD6833. A value of ‘0’ indicates that an external clock is not available to the CL-PD6833. Bit 31 — RFU (reserved for future use) ...
Page 167
... CL-PD6833 PCI-to-CardBus Host Adapter 12. TIMING REGISTERS Table 12-1. Timing Registers Quick Reference Register Name Setup Timing 0–1 Command Timing 0–1 Recovery Timing 0–1 The following information about the timing registers is important: All timing registers take effect immediately and should only be changed when the FIFO is empty (see the ...
Page 168
... Command Timing 1 Table 2-2 on page 15) active time is, in terms of the number of internal val Section 15.3.3 from 0 to 63; it controls the length that a command is val CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: 365 Bit 2 Bit 1 Bit 0 Equation 12-2 for further discussion). ...
Page 169
... CL-PD6833 PCI-to-CardBus Host Adapter 12.3 Recovery Timing 0–1 Register Name: Recovery Timing 0–1 I/O Index: 3Ch, 3Fh Memory Offset: 83Ch, 83Fh Bit 7 Bit 6 Reserved R:00 There are two separate Recovery Timing registers, each with identical fields. These registers are located at the following indexes: ...
Page 170
... TIMING REGISTERS PCI-to-CardBus Host Adapter Notes ADVANCE DATA BOOK v0.3 CL-PD6833 June 1998 ...
Page 171
... CL-PD6833 PCI-to-CardBus Host Adapter 13. DMA OPERATION REGISTERS Table 13-1. DMA Operation Registers Quick Reference Register Name Low Address Mid Low Address Mid High Address High Address Low Count Mid Count High Count DMA Command and Status Request Register Mode Register Master Clear Mask Register This chapter discusses the DMA registers used to make PCI/Way DMA operate ...
Page 172
... Bit 3 Low Address 8 bit 7:0 16 bit 8:1 R/W:00000000 Bit 5 Bit 4 Bit 3 Mid Low Address 8 bit 15:8 16 bit 16:9 R/W:00000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: DMA Bit 2 Bit 1 Bit 0 Register Per: socket Register Compatibility Type: DMA Bit 2 Bit 1 Bit 0 When bits 2:1 of the DMA Slave June 1998 ADVANCE DATA BOOK v0 ...
Page 173
... This register is enabled by bit 3 of the DMA Slave Configuration register. If bit 3 of the DMA Slave Configuration is reset, then address bits 31:24 are ‘00’ during DMA transfers from the CL-PD6833 to memory. June 1998 ADVANCE DATA BOOK v0.3 ...
Page 174
... R/W:00000000 Bit 5 Bit 4 Bit 3 Mid Count 15:8 R/W:00000000 Bit 5 Bit 4 Bit 3 High Count 23:16 R/W:00000000 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: DMA Bit 2 Bit 1 Bit 0 Register Per: socket Register Compatibility Type: DMA Bit 2 Bit 1 Bit 0 Register Per: socket ...
Page 175
... CL-PD6833 PCI-to-CardBus Host Adapter 13.8 DMA Command and Status Register Name: DMA Command and Status I/O Index: 8h Bit 7 Bit 6 Extended DACK Sense DREQ Sense Write Select R:0 R:0 Bit 0 — Mem-to-Mem Enable Reads from this bit return terminal count. Bit 1 — Address Hold Enable Reads from this bit return terminal count. Bit 2 — ...
Page 176
... If the transfer mode bits are set to do block transfers, this bit initiates transfers with no hardware request present on the PC Card interface. Bits 7:3 — Reserved 176 DMA OPERATION REGISTERS Bit 5 Bit 4 Bit 3 CL-PD6833 PCI-to-CardBus Host Adapter Register Per: socket Register Compatibility Type: DMA Bit 2 Bit 1 Bit 0 Set Request ...
Page 177
... CL-PD6833 PCI-to-CardBus Host Adapter 13.10 Mode Register Register Name: Mode Register I/O Index: Bh Bit 7 Bit 6 Address Request Mode Decrement R/W:00 R/W:0 This register emulates the mode register of the Intel 8237. Unlike the Intel 8237 mode register, this register is readable. Bits 1:0 — Channel Number (Ignored) Writes to these bits have no effect. These bits read back what was written to them. Bits 3:2 — ...
Page 178
... This register emulates the Master Clear register of the Intel 8237. Unlike the Intel 8237, there is no temporary register to read back, so read back is not supported. When this register is written, the DMA section of the CL-PD6833 assumes the same state as caused by PCI_RST. The DMA Slave Configuration register is unaffected by writes to this register. ...
Page 179
... CL-PD6833 card socket is operating in ATA mode. Refer to the Cirrus Logic application note Configuring PCMCIA Sockets for ATA Drive Interface (AN-PD5) for more information. All register functions of the CL-PD6833 are available in ATA mode, including socket power control, inter- face signal disabling, and card window control. No memory operations are allowed in ATA mode. ...
Page 180
... D12 55 D13 56 D14 57 D15 58 -CS1 59 VS1 60 -IORD 61 -IOWR 62 n/c 63 n/c 64 n/c 65 n/c 66 n/c 67 VCC 68 CL-PD6833 PCI-to-CardBus Host Adapter (cont.) Function PC Card ATA Interface Interface VPP2 n/c A22 n/c A23 VU A24 -M/S A25 CSEL VS2 VS2 RESET RESET* -WAIT IOCHRDY -INPACK DREQ -REG -DACK -SPKR -LED ...
Page 181
... CL-PD6833 PCI-to-CardBus Host Adapter 15. ELECTRICAL SPECIFICATIONS 15.1 Absolute Maximum Ratings Description Ambient temperature under bias Storage temperature Voltage on any pin (with respect to ground) Operating power dissipation Power dissipation during Suspend mode Power supply voltage Injection current (latch up) a Stresses above those listed may cause permanent damage to system components. These are stress ratings only ...
Page 182
... V 3.0 3.6 V 2.0 V 0.8 V 2.4 V SOCKET_VCC – 0 ADVANCE DATA BOOK v0.3 CL-PD6833 PCI-to-CardBus Host Adapter Conditions Normal operation V core voltage = 3 core voltage = 3 rated respective SOCKET_VCC = 3 rated I , OHC respective SOCKET_VCC = 3 rated I OL Respective SOCKET_VCC = 3 2 Respective SOCKET_VCC = 3 ...
Page 183
... CL-PD6833 PCI-to-CardBus Host Adapter Table 15-3. PCI Bus Interface DC Specifications Symbol Parameter PCI_VCC Power supply voltage 5V PCI_VCC Input high voltage Input low voltage IL V Output high voltage OH V Output high voltage CMOS OHC V Output low voltage OL Output current high ...
Page 184
... MIN MAX Unit MIN TYP MAX tbd tbd tbd tbd tbd ADVANCE DATA BOOK v0.3 CL-PD6833 PCI-to-CardBus Host Adapter (cont.) Conditions ISA_V = 3 0 4.5 V Unit Conditions CORE_VDD = 3.3 V; +5V, SOCKET_VCC, and mA PCI_VCC = 5 < DISS CORE_VDD = 3.3 V; ...
Page 185
... PCI-to-CardBus Host Adapter 15.3 AC Timing Specifications This section includes system timing requirements for the CL-PD6833. Unless otherwise specified, timings are provided in nanoseconds (ns), at TTL input levels, with the ambient temperature varying from and V varying from 5.5 V DC. The PCI bus speed is 33 MHz, unless CC otherwise specifi ...
Page 186
... PCI_VCC = 3.3 V PCI_VCC = 5.0 V MIN MAX MIN MAX 7 – – – – – – – 7 – 11 – 1 – 1 ADVANCE DATA BOOK v0.3 CL-PD6833 Units – ns – ns – ns – – ns – ns – – PCI_CLK June 1998 ...
Page 187
... CL-PD6833 PCI-to-CardBus Host Adapter PCI_CLK FRAME# AD[31:0] Address Write Cycle t 2 AD[31:0] Address Read Cycle t 6 Bus C/BE[3:0]# Command High-Z DEVSEL# High-Z TRDY# High-Z STOP# High-Z = high-impedance Figure 15-1. FRAME#, AD[31:0], C/BE[3:0]#, and DEVSEL# (PCI June 1998 ADVANCE DATA BOOK v0 Data ...
Page 188
... PCI-to-CardBus Host Adapter PCI_VCC = 3.3 V PCI_VCC = 5.0 V MIN MAX MIN – 11 – – 11 – 1 – 1 – 11 – – 11 – 1 – Bus) ADVANCE DATA BOOK v0.3 CL-PD6833 Units MAX – PCI_CLK – PCI_CLK 3 High High-Z June 1998 ...
Page 189
... CL-PD6833 PCI-to-CardBus Host Adapter Table 15-9. IDSEL Timing in a Configuration Cycle Symbol t IDSEL setup to PCI_CLK 1 t IDSEL hold from PCI_CLK 2 PCI_CLK IDSEL FRAME# High-Z AD[7:0] High-Z C/BE[3:0]# High-Z = high-impedance Figure 15-3. IDSEL Timing in a Configuration Cycle (PCI June 1998 ADVANCE DATA BOOK v0.3 ...
Page 190
... PAR Timing (PCI Bus) Symbol t PAR setup to PCI_CLK (input to the CL-PD6833 PAR hold from PCI_CLK (input to the CL-PD6833 PAR valid delay from PCI_CLK (output from the CL-PD6833 PAR hold from PCI_CLK (output from the CL-PD6833) 4 PCI_CLK FRAME# High-Z AD[31:0] ...
Page 191
... CL-PD6833 PCI-to-CardBus Host Adapter 15.3.2 System Interrupt Timing Table 15-11. Pulse Mode Interrupt Timing Symbol t IRQ[XX] low or high 1 High-Z IRQ[XX] High-Z = high-impedance Figure 15-5. Pulse Mode Interrupt Timing June 1998 ADVANCE DATA BOOK v0.3 Parameter MIN MAX Units 15 18 PCI_CLK High-Z 191 ...
Page 192
... If PCI_CLK is selected (Misc Control 2 register bit ‘0’) and operates at 33 MHz, and the clock input is not being divided (Misc Control 2 register bit ‘0’), then: The timing diagrams that follow were derived for a CL-PD6833 using the PCI clock at 33 MHz. The examples for the default values of the Timing registers for Timer Set 0 are as follows: ...
Page 193
... CL-PD6833 PCI-to-CardBus Host Adapter 15.3.4 PC Card (PCMCIA) Bus Timing Table 15-12. Memory Read/Write Timing Symbol t -REG, -CE[2:1], Address, and Write Data setup to Command 1 1 active t Command pulse width 2 t Address hold and Write Data valid from Command inactive 3 t -WAIT active from Command active ...
Page 194
... ELECTRICAL SPECIFICATIONS Parameter see val CL-PD6833 PCI-to-CardBus Host Adapter MIN MAX (S Tcp) – Tcp) – Tcp) – – 2)Tcp – 10 ...
Page 195
... CL-PD6833 PCI-to-CardBus Host Adapter -REG, A[25:0] -IOWR, -IORD -WAIT -IOIS16 -CE1 -CE2 D[15:0] Write Cycle D[15:0] Read Cycle June 1998 ADVANCE DATA BOOK v0 ref Figure 15-7 ...
Page 196
... Figure 15-8. PC Card (PCMCIA) Read/Write Timing (8-Bit System) 196 ELECTRICAL SPECIFICATIONS Parameter see val Odd/Even Data Odd/Even Data XX CL-PD6833 PCI-to-CardBus Host Adapter MIN MAX (S Tcp) – Tcp) – Tcp) – Tcp page 192 see page 192 ...
Page 197
... CL-PD6833 PCI-to-CardBus Host Adapter Table 15-15. Normal Byte Read/Write Timing Symbol t Address setup to Command active 1 t Command pulse width 2 t Address hold from Command inactive 3 1 The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set 0 default value of 00h, the setup time would ...
Page 198
... ELECTRICAL SPECIFICATIONS Parameter see val Odd Data XX CL-PD6833 PCI-to-CardBus Host Adapter MIN MAX (3Tcp Tcp) – Tcp) – Tcp) – 10 page 192 see page 192. val + 1, see page 192. ...
Page 199
... Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. June 1998 ADVANCE DATA BOOK v0.3 30.35 (1.195) 30.85 (1.215) 27.90 (1.098) 28.10 (1.106) 0.13 (0.005) 0.28 (0.011) CL-PD6833 208-Pin MQFP Pin 1 Indicator 25.50 (1.004) REF 3.17 (0.125) 0.40 (0.016) 3.67 (0.144) 0.75 (0.030) 27.90 (1.098) 28.10 (1.106) 25 ...
Page 200
... Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 200 PACKAGE SPECIFICATIONS 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011) CL-PD6833 208-Pin LQFP Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) CL-PD6833 PCI-to-CardBus Host Adapter 27.80 (1.094) 28.20 (1.110) 1.00 (0.039) BSC 0 MIN 7 MAX 0.05 (0.002) 0.15 (0.006) June 1998 ADVANCE DATA BOOK v0.3 ...