cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 101

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

CL-PD6833
PCI-to-CardBus Host Adapter
8.7
Bit 0 — Memory Map 0 Enable
Bit 1 — Memory Map 1 Enable
Bit 2 — Memory Map 2 Enable
Bit 3 — Memory Map 3 Enable
Bit 4 — Memory Map 4 Enable
Bit 5 — Compatibility Bit
June 1998
Register Name: Mapping Enable
I/O Index: 06h
Memory Offset: 806h
I/O Map 1
Enable
R/W:0
Bit 7
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 0 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 1 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 2 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 3 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 4 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
Mapping Enable
0
1
0
1
0
1
0
1
0
1
ADVANCE DATA BOOK v0.3
I/O Map 0
Enable
R/W:0
Bit 6
Memory Window Mapping registers for Memory Window 0 disabled.
Memory Window Mapping registers for Memory Window 0 enabled.
Memory Window Mapping registers for Memory Window 1 disabled.
Memory Window Mapping registers for Memory Window 1 enabled.
Memory Window Mapping registers for Memory Window 2 disabled.
Memory Window Mapping registers for Memory Window 2 enabled.
Memory Window Mapping registers for Memory Window 3 disabled.
Memory Window Mapping registers for Memory Window 3 enabled.
Memory Window Mapping registers for Memory Window 4 disabled.
Memory Window Mapping registers for Memory Window 4 enabled.
Compatibility
Bit 5
R:0
Memory Map
4 Enable
R/W:0
Bit 4
Memory Map
3 Enable
R/W:0
Bit 3
Memory Map
2 Enable
R/W:0
Bit 2
DEVICE CONTROL REGISTERS
Register Compatibility Type: 365
Memory Map
1 Enable
R/W:0
Bit 1
Register Per: socket
Memory Map
0 Enable
R/W:0
Bit 0
101