cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 70

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

5.17
This is the DMA I/O base address for the DMA registers.
Bit 0 — Channel Enable
Bits 2:1 — Transfer Size
Bit 3 — Non-Legacy Extended Addressing
Bits 31:4 — DMA I/O Base Address
70
Byte 3
Byte 2
Byte 1
Byte 0
This bit, along with the DREQ Enable bits in Extension Control 1, enables the DMA channel.
When this bit is ‘0’, DMA operations are not allowed. If both of the DREQ Enable bits in Extension
Control 1 are ‘0’s, DMA operations are not allowed.
These bits define the size of the DMA transfer at the PC Card 16 (R2) socket.
a
When this bit is set to ‘1’, it enables use of the DMA extended addressing.
These bits are used to define the I/O address where the DMA Operation registers can be located.
PCI CONFIGURATION REGISTERS
DMA Slave Configuration Register
These two settings are implemented for compatibility with current R2 conventions.
Offset: 90h
Bit 2
Register Name: DMA Slave Configuration Register
0
0
1
1
Bit 31
Bit 23
Bit 15
Bit 7
DMA I/O Base Address (low)
Bit 30
Bit 22
Bit 14
Bit 6
Bit 1
0
1
0
1
R/W:0000
Bit 29
Bit 21
Bit 13
Size of DMA Transfer at the PC Card 16 (R2) Socket
Bit 5
DMA I/O Base Address (high mid.)
DMA I/O Base Address (low mid.)
DMA I/O Base Address (high)
Bit 28
Bit 20
Bit 12
16-bit transfers at the PC Card
16-bit transfers at the PC Card
Bit 4
16-bit transfers at the PC Card
8-bit transfer at the PC Card
R/W:00000000
R/W:00000000
R/W:00000000
Non-Legacy
Addressing
Extended
R/W:0
Bit 27
Bit 19
Bit 11
Bit 3
ADVANCE DATA BOOK v0.3
Bit 26
Bit 18
Bit 10
Bit 2
PCI-to-CardBus Host Adapter
a
a
Transfer Size
R/W:00
Bit 25
Bit 17
Register Per: socket
Bit 9
Bit 1
CL-PD6833
June 1998
Channel
Enable
R/W:0
Bit 24
Bit 16
Bit 8
Bit 0