cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 163

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

CL-PD6833
PCI-to-CardBus Host Adapter
11.9.5
All bits of this byte are read/write. Device reset defaults are specific to each device. A BIOS write to this
byte before bringing of socket services sets these bits to reflect which of these features are supported in
the system implementation.
Bit 0 — Sockets Present 0
Bit 1 — Sockets Present 1
Bit 2 — Slave DMA Wired
Bit 3 — VS1/VS2 Wired
Bits 5:4 — GPSTB [B:A] Wired
Bit 6 — Hardware Suspend Wired
Bit 7 — RI_OUT Wired
June 1998
RI_OUT Wired
Register Name: Device Implementation Byte A
I/O Index: 38h
Memory Offset: 938h
R/W:0
Bit 7
Bits 1:0 indicate the socket features supported in the system implementation.
This bit indicates whether the system is wired to allow the slave DMA feature to be used.
When this bit is ‘1’, the system is wired to use the VS1/VS2 pin. When this bit is ‘0’ the system is
not wired and is not capable of using the VS1/VS2 pin.
Bits 5:4 indicate the general-purpose strobe features supported in the system implementation.
A ‘1’ indicates that a pin on the device designated as a hardware control of suspend for deep
power saving has been connected to system circuitry designed for power management.
A ‘1’ indicates that a pin on the device designated as ‘RI_OUT’ has been connected to ring indicate
circuitry. Socket services must set the Misc. Control 2 register (I/O index 1E) bit 7 to a ‘1’, thereby
enabling this alternate pin definition as it has been wired.
A value of ‘1’ implies that the RI_OUT*/INTB# pin is not connected to the PCI bus INTB# line, but
is instead connected to an SMI type system function designed to wake up a system on modem
ring.
Device Implementation Byte A
ADVANCE DATA BOOK v0.3
Hardware
Suspend
R/W:0
Wired
Bit 6
GPSTB B
R/W:0
Wired
Bit 5
GPSTB A
R/W:0
Wired
Bit 4
VS1/VS2
R/W:1
Wired
Bit 3
Slave DMA
R/W:0
Wired
Bit 2
Register Compatibility Type: ext.
EXTENSION REGISTERS
Present 1
Sockets
R/W:0
Bit 1
Register Per: chip
Present 0
Sockets
R/W:1
Bit 0
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