cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 80

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

6.4
The Event Force register is a phantom register. These bits are merely control bits. They are not registered
and need no clearing. They provide software the ability to force various status and event bits in the
CL-PD6833. This gives software the ability to test and restore status. Writing ‘1’ to a bit in this register sets
the corresponding bit in the Status Event register and/or the Present State register. Bits 3:0 generate
Management Interrupt if the correct Mask bit is set.
Bit 0 — CSTSCHG/WAKEUP
Bit 1 — CCD1 Changed
Bit 2 — CCD2 Changed
Bit 3 — Power Cycle
Bit 4 — 16-Bit PC Card
80
Byte 3
Byte 2
Byte 1
Byte 0
This bit sets the Card Status Change bit in the Status Event register. The Present State register
remains unchanged.
This bit sets the CCD1 bit in the Status Event register. The Present State register remains
unchanged.
This bit sets the CCD2 bit in the Status Event register. The Present State register remains
unchanged.
This bit sets the Power Cycle bit in the Status Event register. The Present State register remains
unchanged.
This bit sets the 16-bit PC Card bit in the Present State register. If a card is installed in the socket,
writes to this bit are ignored.
CARDBUS REGISTERS
Event Force
Memory Offset: 00Ch
Not a Card
Reserved
Register Name: Event Force
Bit 31
Bit 23
Bit 15
Bit 7
W:0
W:0
Reserved
CV Test
Bit 30
Bit 22
Bit 14
Bit 6
W:0
W:0
CardBus PC
Bit 29
Bit 21
Bit 13
Card
Bit 5
Y-V
W:0
W:0
16-Bit PC
Bit 28
Bit 20
Bit 12
Card
Bit 4
X-V
W:0
W:0
R:00000000
R:00000000
Reserved
Reserved
Power Cycle
3.3-V Card
Bit 27
Bit 19
Bit 11
Bit 3
W:0
W:0
ADVANCE DATA BOOK v0.3
Changed
5-V Card
CCD2
Bit 26
Bit 18
Bit 10
Bit 2
PCI-to-CardBus Host Adapter
W:0
W:0
Changed
Bad V
Request
CCD1
Bit 25
Bit 17
Register Per: socket
Bit 9
Bit 1
W:0
W:0
CC
CL-PD6833
CSTSCHG/
WAKEUP
Data Lost
June 1998
Bit 24
Bit 16
Bit 8
Bit 0
W:0
W:0