cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 77

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

CL-PD6833
PCI-to-CardBus Host Adapter
6.2
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
This register gives software the ability to control the events that can cause interrupts. If the Card Detect
Changed bit is enabled at the time a card is removed, an interrupt is generated. This register is cleared
automatically when card is removed. If the CL-PD6833 is required to generate an interrupt when a new
card is inserted, software must again set the Card Detect Changed mask bit.
Bit 0 — CSTSCHG/WAKEUP (Card Status Change / Wakeup)
Bit 1 — CCD1 Changed
Bit 2 — CCD2 Changed
Bit 3— Power Cycle Complete
Bits 31:4 — Reserved
June 1998
Byte 3
Byte 2
Byte 1
Byte 0
when the CL-PD6833 changes power states from D3 to D0 by a software PCI Bus Segment reset.
When set, this bit enables an interrupt based on the CSTSCHG signal being asserted by a
CardBus card. CSTSCHG interrupts generated by 16-bit cards are controlled by registers in that
interface’s register space. This bit is disabled when it is ‘0’.
When set, this bit enables an interrupt when the CL-PD6833 detects change.
When set, this bit enables an interrupt when the CL-PD6833 detects change.
When set, this bit causes the CL-PD6833 to generate an interrupt 256 cycles of the PCI clock after
powering up a socket.
Status Mask — PME_CXT
Memory Offset: 004h
Register Name: Status Mask — PME_CXT
ADVANCE DATA BOOK v0.3
Bit 31
Bit 23
Bit 15
Bit 7
Bit 30
Bit 22
Bit 14
Bit 6
Reserved
R:0000
Bit 29
Bit 21
Bit 13
Bit 5
Bit 28
Bit 20
Bit 12
Bit 4
R:00000000
R:00000000
R:00000000
Reserved
Reserved
Reserved
Complete
Power
Cycle
R/W:0
Bit 27
Bit 19
Bit 11
Bit 3
Changed
CCD2
R/W:0
Bit 26
Bit 18
Bit 10
Bit 2
CARDBUS REGISTERS
Changed
CCD1
R/W:0
Bit 25
Bit 17
Register Per: socket
Bit 9
Bit 1
CSTSCHG/
WAKEUP
R/W:0
Bit 24
Bit 16
Bit 8
Bit 0
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