cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 61
cl-pd6833
Manufacturer Part Number
cl-pd6833
Description
Pci-to-cardbus Host Adapter
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CL-PD6833.pdf
(216 pages)
- Current page: 61 of 216
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CL-PD6833
PCI-to-CardBus Host Adapter
5.11
Bits 1:0 — Reserved
Bits 15:2 — I/O Limit 15:2
Bits 31:16 — I/O Limit 31:16
June 1998
Byte 3
Byte 2
Byte 1
Byte 0
These bits are reserved and always read back ‘00’.
These bits define the top of an address range of a PCI I/O window to be mapped to a CardBus-
capable PCI I/O space. These bits correspond to PCI I/O address bits 15:2.
These bits read all ‘0’s to be compatible with the CL-PD6832.
I/O Limit 0–1
Offset: 30h, 38h
Register Name: I/O Limit 0–1
ADVANCE DATA BOOK v0.3
Bit 31
Bit 23
Bit 15
Bit 7
Bit 30
Bit 22
Bit 14
Bit 6
Bit 29
Bit 21
Bit 13
Bit 5
R/W:000000
I/O Limit 7:2
Bit 28
Bit 20
Bit 12
Bit 4
R/W:00000000
I/O Limit 31:24
I/O Limit 23:16
I/O Limit 15:8
R:00000000
R:00000000
Bit 27
Bit 19
Bit 11
Bit 3
PCI CONFIGURATION REGISTERS
Bit 26
Bit 18
Bit 10
Bit 2
Bit 25
Bit 17
Register Per: socket
Bit 9
Bit 1
Reserved
R:00
Bit 24
Bit 16
Bit 8
Bit 0
61
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