cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 55

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

CL-PD6833
PCI-to-CardBus Host Adapter
5.6
NOTE: The CardBus (Secondary) Status bytes are similar to the Status bytes in the Command and Status regis-
Bits 7:0 — Power Capabilities Pointer
Bits 23:8 — Reserved
Bit 24 — Secondary Bus Data Parity Error Reported
Bits 26:25 — Reserved
Bit 27 — Signalled Target Abort
Bit 28 — Received Target Abort
June 1998
Status (high)
Status (low)
CardBus
CardBus
Byte 3
Byte 2
Byte 1
Byte 0
ter, but contain information relating to the CardBus. Bit 30 is defined differently than in the Command and
Status register. These bits are reset by PCI reset and by writing ‘1’ to the bit.
This value indicates that the CardBus Controller Power Management registers begin at offset
80h in this configuration space.
This bit is used to report the receipt of PERR# on the PC Card 32 bus. Write a ‘1’ to this bit to clear
it.
To clear this bit, software must write a ‘1’ to it.
To clear this bit, software must write a ‘1’ to it.
CardBus Status
Address/Data
Offset: 14h
0
1
0
1
Parity Error
Register Name: CardBus Status
ADVANCE DATA BOOK v0.3
Detected
Bit 31
Bit 23
Bit 15
RC:0
Bit 7
No target device has signalled a target abort.
A target device has signalled a target abort.
No master transaction has been terminated with a target abort.
A master transaction has been terminated with a target abort.
System Error
Received
(SERR#)
Bit 30
Bit 22
Bit 14
RC:0
Bit 6
Master Abort
Received
Bit 29
Bit 21
Bit 13
RC:0
Bit 5
Target Abort
Power Capabilities Pointer
Received
Bit 28
Bit 20
Bit 12
RC:0
Bit 4
R:00000000
R:00000000
R:10000000
Reserved
Reserved
Target Abort
Signalled
Bit 27
Bit 19
Bit 11
RC:0
Bit 3
PCI CONFIGURATION REGISTERS
Bit 26
Bit 18
Bit 10
Bit 2
Reserved
R:00
Bit 25
Bit 17
Register Per: socket
Bit 9
Bit 1
Parity Error
Secondary
Bus Data
Reported
Bit 24
Bit 16
RC:0
Bit 8
Bit 0
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