cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 54
cl-pd6833
Manufacturer Part Number
cl-pd6833
Description
Pci-to-cardbus Host Adapter
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CL-PD6833.pdf
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5.5
This is the PCI memory address space base address for the Operation registers.
Bit 0 — Memory Space Indicator
Bits 2:1 — Type
Bit 3 — Prefetchable
Bits 31:4 — Controller Memory Base Address
54
Byte 3
Byte 2
Byte 1
Byte 0
This bit always reads back ‘0’, indicating that this base address register defines a PCI memory
space.
These bits indicate that the controller can be located anywhere in the 32-bit address space.
This bit indicates that the Controller registers are not prefetchable.
This field specifies the memory-mapped register space of the CL-PD6833. The Operation
registers can be accessed through this window only after these bits are set to a non-zero value.
PCI CONFIGURATION REGISTERS
Memory Base Address
Offset: 10h
Register Name: Memory Base Address
Bit 31
Bit 23
Bit 15
Bit 7
Controller Memory Base Address (low mid.)
Controller Memory Base Address (low)
Bit 30
Bit 22
Bit 14
Bit 6
R/W:0000
R:0000
Bit 29
Bit 21
Bit 13
Bit 5
Controller Memory Base Address (high mid.)
Controller Memory Base Address (high)
Bit 28
Bit 20
Bit 12
Bit 4
R/W:00000000
R/W:00000000
Prefetchable
Bit 27
Bit 19
Bit 11
Bit 3
R:0
Controller Memory Base Address (low mid.)
ADVANCE DATA BOOK v0.3
Bit 26
Bit 18
Bit 10
Bit 2
PCI-to-CardBus Host Adapter
R:0000
Type
R:00
Bit 25
Bit 17
Register Per: socket
Bit 9
Bit 1
CL-PD6833
June 1998
Indicator
Memory
Space
Bit 24
Bit 16
Bit 8
Bit 0
R:0
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