cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 13

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

CL-PD6833
PCI-to-CardBus Host Adapter
2.3
Table 2-1.
June 1998
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
IDSEL
DEVSEL#
PERR#
Pin Name
Pin Descriptions
PCI Bus Interface Pins
ADVANCE DATA BOOK v0.3
PCI Bus Address / Data Input/Outputs: These pins
connect to PCI bus signals AD[31:0].
PCI Bus Command / Byte Enables: The command
signalling and byte enables are multiplexed on the
same pins. During the address phase of a transaction,
C/BE[3:0]# are interpreted as the bus commands.
During the data phase, C/BE[3:0]# are interpreted as
byte enables. The byte enables are valid for the
entirety of each data phase, and they indicate which
bytes in the 32-bit data path carry meaningful data for
the current data phase.
Cycle Frame: This signal, driven by current master,
indicates that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue. When
FRAME# is deasserted, the transaction is in its final
phase.
Initiator Ready: This signal indicates the initiating
agent’s ability to complete the current data phase of
the transaction. IRDY# is used in conjunction with
TRDY#.
Target Ready: This signal indicates the target agent’s
ability to complete the current data phase of the trans-
action. TRDY# is used in conjunction with IRDY#.
Stop: This signal indicates the current target is
requesting the master to stop the current transaction.
Lock Transaction: This signal is used by a PCI mas-
ter to perform a locked transaction to a target memory.
LOCK# is used to prevent more than one master from
using a particular system resource.
Initialization Device Select: This input is used as a
chip select during configuration read and write trans-
a c t i o n s. T h i s i s a p o i n t - t o - p o i n t s i g n a l . T h e
CL-PD6833 must be connected to its own unique
IDSEL line (from the PCI bus arbiter or one of the
most-significant AD bus pins).
Device Select: When actively driven, this signal indi-
cates that it has decoded its own PCI address as the
target of the current access. As an input, DEVSEL#
indicates to the CL-PD6833 whether any device on
the bus has been selected.
Parity Error: The CL-PD6833 drives this output
active (low) if it detects a data parity error during a
write phase.
Description
16–20, 22–24,
38–43, 45–46,
Pin Number
48–49, 51–56
13, 25, 36, 47
4–5, 7–12,
27
29
30
32
58
15
31
33
Qty.
32
4
1
1
1
1
1
1
1
1
PIN INFORMATION
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Pwr.
4
4
4
4
4
4
4
–
4
4
Drive
Spec.
Spec.
Spec.
Spec.
Spec.
Spec.
Spec.
Spec.
Spec
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
–
13