cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 82

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

6.5
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
The Socket Control register provides control of the socket’s V
to ‘0’ by RST# and power removed from the socket. This register is write-protected by writes to bits 13:10
of the Event Force register, and not write-protected on completion of the decoding sequence of the CD1,
CD2, VS1, and VS2 lines or completion of CV test. Use either this register or the Power Control register
(index 02h) for power control. Do not use both registers.
Bits 2:0 — V
82
Byte 3
Byte 2
Byte 1
Byte 0
when the CL-PD6833 changes power states from D3 to D0 by a software PCI Bus Segment reset.
These bits are used to switch the V
no knowledge of a card’s V
from the card’s CIS. The following table shows the V
bits.
CARDBUS REGISTERS
Control — PME_CXT
Bit 2
0
0
0
0
Memory Offset: 010h
Stop Clock
Register Name: Control — PME_CXT
PP
R/W:0
Bit 31
Bit 23
Bit 15
Bit 7
Control
100—111
Bit 1
0
0
1
1
Bit 30
Bit 22
Bit 14
Bit 6
Bit 0
0
1
0
1
PP
V
CC
R/W:000
voltage requirement. Software must determine the needed voltage
Bit 29
Bit 21
Bit 13
Bit 5
Control
PP
power using external V
Bit 28
Bit 20
Bit 12
Bit 4
R:00000000
R:00000000
R:00000000
Reserved
Reserved
Reserved
V
PP
PP
Reserved
Reserved
Requested
12.0 V
5.0 V
3.3 V
Bit 27
Bit 19
Bit 11
Bit 3
0 V
R:0
requested depending on the setting of the
CC
and V
PP
ADVANCE DATA BOOK v0.3
control logic. The CL-PD6833 has
PP
Bit 26
Bit 18
Bit 10
Bit 2
PCI-to-CardBus Host Adapter
. All bits in this register are set
V
PP
R/W:000
Bit 25
Bit 17
Register Per: socket
Bit 9
Bit 1
Control
CL-PD6833
June 1998
Bit 24
Bit 16
Bit 8
Bit 0