cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 4

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

6.
7.
8.
9.
10. GENERAL WINDOW MAPPING REGISTERS.................................................................. 117
4
CARDBUS REGISTERS ...................................................................................................... 75
6.1
6.2
6.3
6.4
6.5
OPERATION REGISTERS ................................................................................................... 85
7.1
7.2
DEVICE CONTROL REGISTERS........................................................................................ 91
8.1
8.2
8.3
8.4
8.5
8.6
8.7
WINDOW MAPPING REGISTERS..................................................................................... 103
9.1
9.2
10.1 General Mapping Registers for I/O Mode ..........................................................................................119
10.2 General Mapping Register for Memory Mode ....................................................................................125
TABLE OF CONTENTS
Status Event — PME_CXT .................................................................................................................. 75
Status Mask — PME_CXT................................................................................................................... 77
Present State ....................................................................................................................................... 78
Event Force .......................................................................................................................................... 80
Control — PME_CXT ........................................................................................................................... 82
Index .................................................................................................................................................... 85
Data...................................................................................................................................................... 90
Chip Revision ....................................................................................................................................... 91
Interface Status .................................................................................................................................... 92
Power Control — PME _CXT ............................................................................................................... 94
Interrupt and General Control — PME_CXT........................................................................................ 96
Card Status Change — PME_CXT ...................................................................................................... 98
Management Interrupt Configuration — PME_CXT............................................................................. 99
Mapping Enable .................................................................................................................................101
I/O Window Mapping Registers..........................................................................................................105
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
Memory Window Mapping Registers .................................................................................................110
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
10.1.1 Gen Map 0–6 Start Address Low (I/O)..................................................................................119
10.1.2 Gen Map 0–6 Start Address High (I/O).................................................................................120
10.1.3 Gen Map 0–6 End Address Low (I/O) ...................................................................................121
10.1.4 Gen Map 0–6 End Address High (I/O) ..................................................................................122
10.1.5 Gen Map 0–6 Offset Address Low (I/O)................................................................................123
10.1.6 Gen Map 0–6 Offset Address High (I/O) ...............................................................................124
10.2.1 Gen Map 0–6 Start Address Low (Memory) .........................................................................125
10.2.2 Gen Map 0–6 Start Address High (Memory).........................................................................126
10.2.3 Gen Map 0–6 End Address Low (Memory)...........................................................................127
10.2.4 Gen Map 0–6 End Address High (Memory)..........................................................................128
10.2.5 Gen Map 0–6 Offset Address Low (Memory)........................................................................129
10.2.6 Gen Map 0–6 Offset Address High (Memory).......................................................................130
I/O Window Control ...............................................................................................................105
System I/O Map 0–1 Start Address Low ...............................................................................107
System I/O Map 0–1 Start Address High ..............................................................................107
System I/O Map 0–1 End Address Low ................................................................................108
System I/O Map 0–1 End Address High ...............................................................................108
Card I/O Map 0–1 Offset Address Low .................................................................................109
Card I/O Map 0–1 Offset Address High ................................................................................109
System Memory Map 0–4 Start Address Low.......................................................................110
System Memory Map 0–4 Start Address High......................................................................111
System Memory Map 0–4 End Address Low ........................................................................112
System Memory Map 0–4 End Address High .......................................................................113
Card Memory Map 0–4 Offset Address Low .........................................................................114
Card Memory Map 0–4 Offset Address High ........................................................................115
ADVANCE DATA BOOK v0.3
PCI-to-CardBus Host Adapter
CL-PD6833
June 1998