cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 14

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

Table 2-1.
14
SERR#
PAR
PCI_CLK
RST#
INTA#/LED1*/
GPIO1
INTB#/
RI_OUT*/
PME#
Pin Name
PIN INFORMATION
PCI Bus Interface Pins
S y s t e m E r ro r : T h i s o u t p u t i s p u l s e d by t h e
CL-PD6833 to indicate an address parity error.
Parity: This pin is sampled by the clock cycle after
completion of each corresponding address or write
data phase. For read operations, this pin is driven
from the cycle after TRDY# is asserted until the cycle
after completion of each data phase. It ensures even
parity across AD[31:0] and C/BE[3:0]#.
PCI Clock: This input provides timing for all transac-
tions on the PCI bus to and from the CL-PD6833. All
PCI bus interface signals described in this table
(Table
sampled on the rising edge of PCI_CLK; and all the
CL-PD6833 PCI bus interface timing parameters are
defined with respect to this edge. This input can be
operated at frequencies from 0 to 33 MHz.
Device Reset: This input is used to initialize all regis-
ters and internal logic to their reset states and place
all the CL-PD6833 pins in a high-impedance state.
PCI Bus Interrupt A: This output indicates a pro-
grammable interrupt request generated from any of a
number of card actions.
Although there is no specific mapping requirement for
connecting interrupt lines from the CL-PD6833 to the
system, a common use is to connect this pin to the
PCI bus INTA# interrupt line and use PCI Interrupt
Signalling mode (see the register at memory offset
930h,
LED1*: This feature is only available in PCI/Way inter-
rupt signalling mode (see the register at memory off-
set 930h,
General-Purpose Input/Output 1: This pin can also
be used for either input or output under the control of
the GPIO Input Control and GPIO Output Control
registers (see also the Pin Multiplex Control 0 regis-
ter at memory offset 914h). This pin is grouped with
and powered from the PCI_VCC pin.
PCI Bus Interrupt B: In PCI Interrupt Signalling
mode, this output can be used as an interrupt output
connected to the PCI bus INTB# interrupt line.
Ring Indicate Output: If Misc Control 2 register bit 7
is ‘1’, this pin works as a ring indicate output from a
socket’s BVD1/-STSCHG/-RI input. Ring indicate
capability is available in all of the Interrupt Signalling
modes. RI_OUT* and INTB# are open-drain outputs.
Power Management Event: This signal is used to
indicate that a card or the controller needs service
when it is in a power state that prohibits the use of an
interrupt (see also the Pin Multiplex Control 0
register at memory offset 914h).
Misc Control 5 on page
2-1), except RST#, INTA#, and INTB# are
Misc Control 5 on page
Description
(cont.)
158).
158).
Pin Number
207
203
204
34
35
1
ADVANCE DATA BOOK v0.3
PCI-to-CardBus Host Adapter
Qty.
1
1
1
1
1
1
O-TS
O-TS
OD,
I/O
OD
I/O
O-
I
I
CL-PD6833
Pwr.
4
4
–
–
4
4
June 1998
Drive
Spec.
Spec.
Spec.
Spec.
PCI
PCI
PCI
PCI
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