cl-pd6833 Cirrus Logic, Inc., cl-pd6833 Datasheet - Page 113

• Manufacturer Part Number: cl-pd6833
• Description: Pci-to-cardbus Host Adapter
• Manufacturer: Cirrus Logic, Inc.

CL-PD6833
PCI-to-CardBus Host Adapter
9.2.4
There are five separate System Memory Map End Address High registers, each with identical fields.
These registers are located at the following indexes:
Bits 3:0 — End Address 23:20
Bits 5:4 — Scratchpad Bits
Bits 7:6 — Card Timer Select
June 1998
Register Name: System Memory Map 0–4 End Address High
I/O Index: 13h, 1Bh, 23h, 2Bh, 33h
Memory Offset: 813h, 81Bh, 823h, 82Bh, 833h
Index (Socket A)
13h
1Bh
23h
2Bh
33h
Bit 7
Card Timer Select
This field contains the most-significant four bits of the End Address. See the description of the End
Address field associated with bits 7:0 of the System Memory Map 0–4 End Address Low
register. Note that the upper memory addresses are stored in the System Memory Map Upper
Address
This field selects the Timer Set registers to control socket timing for card accesses in this window
address range. This field selects the timer set. Timer Set 0 and 1 reset to values compatible with
PC Card standards. Mapping of bits 7:6 to Timer Set 0 and 1, as shown, is done for software
compatibility with other older ISA-bus based PC Card host adapters that use ISA bus wait states
instead of Timer Set registers.
R/W:00
System Memory Map 0–4 End Address High
Bit 7
0
0
1
1
ADVANCE DATA BOOK v0.3
register.
Bit 6
Bit 6
0
1
0
1
Register
System Memory Map 0 End Address High
System Memory Map 1 End Address High
System Memory Map 2 End Address High
System Memory Map 3 End Address High
System Memory Map 4 End Address High
Bit 5
Scratchpad Bits
Selects Timer Set 0
Selects Timer Set 1
Selects Timer Set 1
Selects Timer Set 1
R/W:00
Bit 4
Bit 3
Timer Set Select
Bit 2
End Address 23:20
WINDOW MAPPING REGISTERS
R/W:0000
Register Compatibility Type: 365
Bit 1
Register Per: socket
Bit 0
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